Showing papers on "Dopant Activation published in 2017"

Low-temperature (330 °C) crystallization and dopant activation of Ge thin films via AgSb-induced layer exchange: Operation of an n-channel polycrystalline Ge thin-film transistor

Abstract: Ge thin films have been prepared by layer-exchange metal-induced crystallization using AgSb alloy as a catalyst. Not only the crystallization of Ge, but also the incorporation of Sb atoms into the crystalline Ge layer and their activation have been realized during the process at a temperature as low as 330 °C. Thin-film transistors have been fabricated using the Ge thin films as channel layers and the operation of an n-channel transistor with an on/off ratio of over 300 has been demonstrated.

Shallow Heavily Doped n++ Germanium by Organo-Antimony Monolayer Doping.

Abstract: Functionalization of Ge surfaces with the aim of incorporating specific dopant atoms to form high-quality junctions is of particular importance for the development of solid-state devices. In this study, we report the shallow doping of Ge wafers with a monolayer doping strategy that is based on the controlled grafting of Sb precursors and the subsequent diffusion of Sb into the wafer upon annealing. We also highlight the key role of citric acid in passivating the surface before its reaction with the Sb precursors and the benefit of a protective SiO2 overlayer that enables an efficient incorporation of Sb dopants with a concentration higher than 1020 cm–3. Microscopic four-point probe measurements and photoconductivity experiments show the full electrical activation of the Sb dopants, giving rise to the formation of an n++ Sb-doped layer and an enhanced local field-effect passivation at the surface of the Ge wafer.

Control of the compensating defects in Al-doped and Ga-doped ZnO nanocrystals for MIR plasmonics

Abstract: In degenerate semiconductor nanoparticles, the tuning range of the plasmon resonance is directly controlled by the electron gas concentration and thus by the dopant activation Here, we investigate the improvement of the dopant activation in ZnO-based nanocrystals for mid IR plasmonics For that purpose, we have synthesized Al-doped and Ga-doped ZnO nanocrystals in O-rich and O-poor environments We show that the free carrier concentration can be doubled for the samples grown in an O-poor environment Accordingly, the plasmon resonance shifts from 5 μm to 31 μm In analogy with previous results from Ga-doped ZnO thin films, we discuss the effect of the possible reduction of the concentration of acceptor-like complexes such as AlZn–VZn and AlZn–Oi (resp GaZn–VZn and GaZn–Oi) on the activation improvement Besides, whether long or rapid, thermal annealing does not improve the compensation ratio Consequently, the control of O content during synthesis remains the most valuable tool to achieve the highest dopant activation in doped ZnO nanocrystals

Ab initio modeling of vacancies, antisites, and Si dopants in ordered InGaAs

Abstract: In0.53Ga0.47As, a III–V compound semiconductor with high electron mobility, is expected to bring better performance than silicon in next-generation n-type MOSFET devices. However, one major challenge to its wide scale adoption is the difficulty of obtaining high enough dopant activation. For Si-doped InGaAs, the best current experimental result, involving 10 min of furnace annealing at temperatures above 700 °C, yields a free electron concentration of 1.4×1019 cm–3, a value that still falls short of requirement for practical applications. In this paper, we investigate the origin of low dopant activation in InGaAs by calculating formation energies for a wide variety of single point defects (Si substutionals, Si tetrahedral interstitials, vacancies, and antisites) in Si-doped In0.5Ga0.5As in a CuAu-I type crystal structure. We find that (1) a high electron concentration can only be achieved under In/Ga-poor growth conditions, while As-poor conditions inhibit n-type doping; and (2) in heavily n-doped samples...

Impact of Thermal Treatments in Crystalline Reconstruction and Electrical Properties of Diamond Ohmic Contacts Created by Boron Ion Implantation

Abstract: To obtain p-type doping of diamond through B ion implantation, thermal treatments are necessary to reconstruct the diamond lattice and to locate B atoms in substitutional lattice positions. The present contribution evaluates by STEM-EELS and CL spectroscopy the amorphisation of diamond lattice under the B+ bombardment and its subsequent reconstruction after the thermal treatment. In addition, TEM observations allowed localizing the boron spatial distribution. Carbon-related peaks of EELS spectroscopy shows a nearly complete recovery of the diamond lattice after thermal treatment. Indeed, at 1600 °C, sp2/sp3 ratio in implanted regions changes from 0.56 to 0.18 (0.15 value was measured before implantation). On the other hand, CL spectroscopy reveals how A-Band and free exciton emission peaks, which are quenched by B+ implantation, recover after annealing. Boron ion implantation was used to create ohmic contacts in two different diamond samples, treated with different annealing velocities. Crystalline reconstruction, evidenced by TEM data explains the related electric behaviour. Nanoscale evidences of amorphisation, lattice reconstruction and dopant activation are presented and discussed in this work.

Modeling of electrical activation ratios of phosphorus and nitrogen doped silicon carbide

Abstract: We propose an empirical model to accurately predict electrical activation ratios of phosphorus and nitrogen implanted silicon carbide for arbitrary annealing temperatures. We introduce model parameters and compare the activation behaviour of the two donor-type dopants. Our investigations show that the activation ratio of the nitrogen implanted silicon carbide is similar to a step function, while the activation ratio for the phosphorus implanted silicon carbide increases continuously with post-implantation annealing temperature. The model has been implemented into Silvaco's Victory Process simulator, which has enabled accurate predictions of dopant activation in postimplantation steps for silicon carbide-based processes. Several simulations have been performed to extract the depth profiles of the active dopant concentrations and to predict the activation as a function of total doping concentration and annealing temperature.

(Invited) Sequential 3D Process Integration: Opportunities for Low Temperature Processing

Abstract: 3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

Dopant activation mechanism of Bi wire-δ-doping into Si crystal, investigated with wavelength dispersive fluorescence x-ray absorption fine structure and density functional theory.

Abstract: We successfully characterized the local structures of Bi atoms in a wire-δ-doped layer (1/8 ML) in a Si crystal, using wavelength dispersive fluorescence x-ray absorption fine structure at the beamline BL37XU, in SPring-8, with the help of density functional theory calculations. It was found that the burial of Bi nanolines on the Si(0 0 1) surface, via growth of Si capping layer at 400 °C by molecular beam epitaxy, reduced the Bi-Si bond length from [Formula: see text] to [Formula: see text] A. We infer that following epitaxial growth the Bi-Bi dimers of the nanoline are broken, and the Bi atoms are located at substitutional sites within the Si crystal, leading to the shorter Bi-Si bond lengths.

Solid solubility limited dopant activation of group III dopants (B, Ga & In) in Ge targeting sub-7nm node low p+ contact resistance

Abstract: Low contact resistance (Rc) is key to boost device performance for sub-10nm node. At VLSI Technology Symposium 2016 Samsung reported they reduced Rc by 10% from 14nm to 10nm bulk FinFET technology [1]. TSMC in their beyond 10nm node FinFET paper reported reducing S/D (source/drain) parasitic resistance and enhanced contact process [2] and at IEDM-2016 reported 7nm FinFET reduced S/D parasitic resistance and developed a novel contact process [3]. A complete session #7 was dedicated to “Contact Resistance Innovations for Sub 10nm Scaling” with 4 papers at the VLSI Technology Symposium 2016 [4-7]. To achieve Rc in the low E-9 Ωcm2 requires active dopant carrier concentration >5E20/cm3 to low E21/cm3. For SiP n+ S/D contacts P >1E21/cm3 active dopant carrier concentration is realized with laser melt annealing resulting in Rc <1E-9 Ωcm2 [6]. For 70%-SiGe p+ S/D contacts IMEC reported using pre and post Ge amorphous implants to boost the B-implant activation with nsec laser melt annealing to reduce Rc from 1.2E-8 Ωcm2 to 2.1E-9 Ωcm2 [4]. IBM/GF on the other hand reported reducing SiGe p+ S/D Rc from 1.3E-8 Ωcm2 to 1.9E-9 Ωcm2 by using a thin 12nm 100%-Ge trench-epi and switching from a p+ Ge:B to a p+ Ge:B:group-III metastable alloy for surface interface doping [8]. The group-III Me-alloy in Ge boosted p+ dopant activation from ∼1E19/cm3 with B to ∼8E20/cm3 with Ge+Me-alloy. They mentioned no difference between msec non-melt and nsec melt laser annealing.

Investigation of silicide-induced-dopant-activation for steep tunnel junction in tunnel field effect transistor (TFET)

Abstract: Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p+ and n+ silicon formed on the p- substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.

Enhanced recrystallization and dopant activation of P+ ion-implanted super-thin Ge layers by RF hydrogen plasma treatment

Abstract: Radio-frequency (RF) hydrogen plasma treatment, thermal annealing in a furnace, and rapid thermal annealing of high-dose P+ ion implanted p-type Ge layers have been studied by Raman scattering spectroscopy, atomic force microscopy, secondary ion mass spectrometry, electrochemical capacitance–voltage profiling, four-point probes method, and x-ray reflectometry. It was shown that low-temperature RF plasma treatment at temperature about 200 °C resulted in full recrystallization of amorphous Ge layer implanted by P+ ions and activation of implanted impurity up to 6.5 × 1019 cm−3 with a maximum concentration at the depth of about 20 nm. Rapid thermal annealing (15 s) and thermal annealing (10 min) in nitrogen ambient required considerably higher temperatures for the recrystallization and activation processes that resulted in diffusion of implanted impurity inside the Ge bulk. It was demonstrated that RF plasma treatment from the samples with front (implanted) side resulted in considerable stronger effects of r...

Iodine Doping of CdTe and CdMgTe for Photovoltaic Applications

Abstract: Iodine-doped CdTe and Cd1−x Mg x Te layers were grown by molecular beam epitaxy. Secondary ion mass spectrometry characterization was used to measure dopant concentration, while Hall measurement was used for determining carrier concentration. Photoluminescence intensity and time-resolved photoluminescence techniques were used for optical characterization. Maximum n-type carrier concentrations of 7.4 × 1018 cm−3 for CdTe and 3 × 1017 cm−3 for Cd0.65Mg0.35Te were achieved. Studies suggest that electrically active doping with iodine is limited with dopant concentration much above these values. Dopant activation of about 80% was observed in most of the CdTe samples. The estimated activation energy is about 6 meV for CdTe and the value for Cd0.65Mg0.35Te is about 58 meV. Iodine-doped samples exhibit long lifetimes with no evidence of photoluminescence degradation with doping as high as 2 × 1018 cm−3, while indium shows substantial non-radiative recombination at carrier concentrations above 5 × 1016 cm−3. Iodine was shown to be thermally stable in CdTe at temperatures up to 600°C. Results suggest iodine may be a preferred n-type dopant compared to indium in achieving heavily doped n-type CdTe.

Ultra-shallow junction formation on 3D silicon and germanium device structures by ion energy decoupled plasma doping

Abstract: Advanced inductively coupled plasma techniques and surface treatments have been used to demonstrate 5 nm conformal shallow junctions at low energy with no structure damage for both silicon (Si) and germanium (Ge). N-type PH 3 plasma-assisted doping was characterized by dopant diffusion and electrical activation with increasing wafer temperature. Plasma-assisted doping at high wafer temperature showed no structure damage even at a high incident energy condition with a bias power applied to the wafer, while a shallow junction with a junction depth (Xj) of less than 5 nm was achieved with low incident energy condition without bias power. Adding Antimony (Sb) in the plasma-assisted doping step when using the decoupled plasma condition was found to enhance the phosphorous (P) dopant level and the activation level dramatically. Various annealing techniques were compared to understand the impact to dopant activation and levels to form shallow junctions of less than 5 nm.

Field effect transistors with reduced parasitic resistances and method

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration

Abstract: We are proposing a double gate junction-less device with a processing temperature compatible with state-of-the-art dense low k dielectric back-end of line copper process. The thermal stability of the back-end of line process was studied, showing no degradation for an anneal temperature up to 500°C 1h. Using wafer bonding, a crystalline silicon layer can be transferred onto a carrier wafer followed by top device processing at low temperature with a gate first approach as well as direct W contacts with Ti/TiN barrier layer. To avoid dopant activation using high temperature anneal (spike), junction-less devices are used, where the uniform channel dopant implantation and activation can be done prior to the layer transfer.

30‐4: Characterization of Si Thin Films Doped by Wet‐Chemical Laser Processing

Abstract: In this paper, we report on the characterization of Si thin films doped by wet-chemical laser processing. Using this method, implantation and dopant activation can be performed simultaneously. After laser doping, the mobility, carrier concentration, and resistivity of the films were 74 cm2/V·s, 5.5 × 1017 cm−3, and 0.15 Ω·cm, respectively.

Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation

Abstract: The influence of extension doping on parasitic resistance and its variability has been investigated for FinFETs. Electrical characterization of FinFETs and crystallinity evaluation of the doped fin structure are carried out for different fin thicknesses and different donor species for ion implantation, i.e., As and P. Reducing the fin thickness and the use of donor species with a larger mass cause serious degradation in the variability and median value of the parasitic resistance. Crystallinity evaluation by transmission electron microscope reveals that significant crystal defects remain after dopant activation annealing for the cases of smaller fin thickness and the implanted dopant with a larger mass. The unrecovered defects cause serious degradation in the parasitic resistance and its variability.

Towards 500°C SPER activated devices for 3D sequential integration

Abstract: This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

High-temperature p-type polarization doped AlGaN cladding for sub-250 nm deep-UV quantum well LEDs by MBE

Abstract: Deep UV (DUV) light-emitting diodes (LEDs) are finding increased application in many areas including water purification and sterilization. Sub-270 nm emission is ideal for these applications since bacterial DNA absorbs strongly in this wavelength regime. To extract high energy photons (∼5 eV), the LED cladding regions must be transparent and therefore consist of high Aluminum content (>60%) n- and p-AlGaN. Ensuring high electrical conductivity in such cladding regions becomes increasingly difficult with increasing Al content due to the large dopant activation energies, especially for the acceptor dopant, Magnesium (Mg) [1]. To maximize Mg incorporation by MBE, a commonly utilized approach is to grow the p-cladding region at a low temperature (∼630 °C [2]). A low growth temperature causes defects and undesired compositional inhomogeneity, leading to inferior vertical hole transport (Fig. 1). To address these issues, a combination of high temperature MBE growth of the p-AlGaN cladding and polarization-induced doping is employed. While high growth temperature ensures good crystal quality and compositional uniformity for the Al-rich p-AlGaN, the polarization-induced doping compensates for the reduced Mg incorporation at high temperature. A sub-250 nm DUV LED is demonstrated for the first time using MBE-grown p-AlGaN layers at a high temperature of 730 °C. SIMS analysis (Fig. 2) showed that Mg incorporation decreases by ∼5 times over the temperature range from 650–730°C for 75% AlGaN, and that Mg incorporation decreases at high Al content, consistent with thermodynamic principles [3]. Based on the observations from Fig. 1 and 2, a substrate temperature of 730 °C was chosen for the p-cladding layer for a sub-250 nm DUV LED structure.

Comparison of scanning laser annealing and microwave annealing for As+ implanted Si

Abstract: Laser annealing and microwave (MW) annealing are rapid annealing techniques that can be used for postannealing of ion implanted semiconductors. In this study, laser annealing and MW annealing of As+ implanted Si are compared in terms of dopant activation, energy absorption, recrystallization, and dopant diffusion. Laser annealing caused similar recrystallization and a slightly higher dopant activation than MW annealing did, at the same time, the energy density absorbed during laser annealing is ∼1/7 lower than during MW annealing, due to surface heating. Rapid dopant activation and negligible dopant diffusion were achieved in the MW annealed sample. This indicates that MW annealing is a promising method for annealing ion implanted source, drain, and channel regions for shallow-junction transistor fabrication. On the other hand, laser annealing results in significant but uniform dopant diffusion, and therefore, laser annealing appears to be beneficial for quickly forming deep wells with uniform dopant conc...

The degradation of high power gallium nitride light-emitting diodes

Abstract: In this paper, the degradation of bare high power GaN/InGaN blue light-emitting diodes (HP-LEDs) was investigated by considering the electrical, thermal and optical aging characteristics. The HP-LED samples were stressed at the elevated temperature of 85 °C with an injection current of 500 mA. The rated current of the HP-LEDs is 350 mA at room temperature. Changing in tunneling current for the electrical characteristic, a gradual increase for the external quantum efficiency (EQE), a gradual decrease for the light power and the luminous flux were monitored. The luminous intensity distribution is more uneven after degradation. And thermal resistance and temperature rise of chip increase with aging time. In addition, the thermal resistance of the die-attach and ceramic wafer were also increasing after aging. After theoretical calculation, the defect concentration of the die monotonously increases with aging time. Therefore, the responsible factors of these changes were proposed to be the generation of the dopant activation, point defects, dislocations and other defects in the chip level during highly accelerated test. These defects as non-radiative recombination centers make charge carrier cross quantum well structure directly. Thereby, the degradation of the electrical, thermal and optical aging characteristics of HP-LEDs is observed.