Showing papers on "Negative impedance converter published in 2016"

Negative Capacitance in a Ferroelectric Capacitor

Abstract: The Boltzmann distribution of electrons poses a fundamental barrier to lowering energy dissipation in conventional electronics, often termed as Boltzmann Tyranny. Negative capacitance in ferroelectric materials, which stems from the stored energy of a phase transition, could provide a solution, but a direct measurement of negative capacitance has so far been elusive. Here, we report the observation of negative capacitance in a thin, epitaxial ferroelectric film. When a voltage pulse is applied, the voltage across the ferroelectric capacitor is found to be decreasing with time--in exactly the opposite direction to which voltage for a regular capacitor should change. Analysis of this 'inductance'-like behaviour from a capacitor presents an unprecedented insight into the intrinsic energy profile of the ferroelectric material and could pave the way for completely new applications.

Negative capacitance in multidomain ferroelectric superlattices

Abstract: The stability of spontaneous electrical polarization in ferroelectrics is fundamental to many of their current applications, which range from the simple electric cigarette lighter to non-volatile random access memories1. Research on nanoscale ferroelectrics reveals that their behaviour is profoundly different from that in bulk ferroelectrics, which could lead to new phenomena with potential for future devices2, 3, 4. As ferroelectrics become thinner, maintaining a stable polarization becomes increasingly challenging. On the other hand, intentionally destabilizing this polarization can cause the effective electric permittivity of a ferroelectric to become negative5, enabling it to behave as a negative capacitance when integrated in a heterostructure. Negative capacitance has been proposed as a way of overcoming fundamental limitations on the power consumption of field-effect transistors6. However, experimental demonstrations of this phenomenon remain contentious7. The prevalent interpretations based on homogeneous polarization models are difficult to reconcile with the expected strong tendency for domain formation8, 9, but the effect of domains on negative capacitance has received little attention5, 10, 11, 12. Here we report negative capacitance in a model system of multidomain ferroelectric–dielectric superlattices across a wide range of temperatures, in both the ferroelectric and paraelectric phases. Using a phenomenological model, we show that domain-wall motion not only gives rise to negative permittivity, but can also enhance, rather than limit, its temperature range. Our first-principles-based atomistic simulations provide detailed microscopic insight into the origin of this phenomenon, identifying the dominant contribution of near-interface layers and paving the way for its future exploitation.

Couplings in Phase Domain Impedance Modeling of Grid-Connected Converters

Abstract: The output impedance of a power converter plays an important role in the stability assessment of the converter. The impedance can be expressed in different frames such as the stationary frame (phase domain) or in the synchronous frame ( dq domain). To treat the three-phase system like a single-phase system, the system can be divided into positive and negative sequences in the phase domain. This paper demonstrates that there exist couplings between the positive and negative sequences, even in a balanced system due to the PLL, which is important for synchronization. Further it will be shown that even though these couplings are very small in magnitude, they are important in the stability of the converter.

Direct Observation of Negative Capacitance in Polycrystalline Ferroelectric HfO2

Abstract: To further reduce the power dissipation in nanoscale transistors, the fundamental limit posed by the Boltzmann distribution of electrons has to be overcome. Stabilization of negative capacitance in a ferroelectric gate insulator can be used to achieve this by boosting the transistor gate voltage. Up to now, negative capacitance is only directly observed in polymer and perovskite ferroelectrics, which are incompatible with semiconductor manufacturing. Recently discovered HfO2-based ferroelectrics, on the other hand, are ideally suited for this application because of their high scalability and semiconductor process compatibility. Here, for the first time, a direct measurement of negative capacitance in polycrystalline HfO2-based thin films is reported. Decreasing voltage with increasing charge transients are observed in 18 and 27 nm thin Gd:HfO2 capacitors in series with an external resistor. Furthermore, a multigrain Landau–Khalatnikov model is developed to successfully simulate this transient behavior in polycrystalline ferroelectrics with nucleation limited switching dynamics. Structural requirements for negative capacitance in such materials are discussed. These results demonstrate that negative capacitance effects are not limited to epitaxial ferroelectrics, thus significantly extending the range of potential applications.

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Abstract: We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length $L_{g}=100$ nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau–Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective $S$ -shaped ferroelectric charge–voltage characteristics that provides important insights into the device operation.

Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching

Abstract: We demonstrate a nearly hysteresis-free sub-60-mV/decade subthreshold swing (SS) operation in a p-type bulk metal–oxide–semiconductor field-effect transistor externally connected to a ferroelectric capacitor. The SS $\mu \text{m}\sim 10$ nA/ $\mu \text{m}$ of drain current) and at large drain current levels. However, the extent of hysteresis is found to be strongly dependent on the drain voltage. At high drain voltages, large hysteresis occurs, indicating the influence of drain voltage in the charge balance with the ferroelectric capacitor.

Structure for multi-input multi-output dc–dc boost converter

Abstract: In this study, a new structure for multi-input multi-output (MIMO) dc-dc boost converter is proposed. The number of inputs and outputs of the converter are arbitrary and independent from each other. The proposed topology has the advantages of both dc-dc boost and switched-capacitor converters. This converter is proper to use in applications like photovoltaic or fuel cell systems. The main advantages of the proposed structure are possibility of using energy supplies with different voltage-current characteristics, continuous input current, high voltage gain without high duty cycle, and possibility of performing at high switching frequencies. First, the different operating modes of the proposed converter are explained. Then, the effect of equivalent series resistance (ESR) of the inductor and voltage drop of diodes and switches on the voltage gain is investigated. Finally, the correctness operation of the proposed converter is reconfirmed by the simulation and experimental results.

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Abstract: We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.

Secondary-Side-Regulated Soft-Switching Full-Bridge Three-Port Converter Based on Bridgeless Boost Rectifier and Bidirectional Converter for Multiple Energy Interface

Abstract: A systematic method for deriving soft-switching three-port converters (TPCs), which can interface multiple energy, is proposed in this paper. Novel full-bridge (FB) TPCs featuring single-stage power conversion, reduced conduction loss, and low-voltage stress are derived. Two nonisolated bidirectional power ports and one isolated unidirectional load port are provided by integrating an interleaved bidirectional Buck/Boost converter and a bridgeless Boost rectifier via a high-frequency transformer. The switching bridges on the primary side are shared; hence, the number of active switches is reduced. Primary-side pulse width modulation and secondary-side phase shift control strategy are employed to provide two control freedoms. Voltage and power regulations over two of the three power ports are achieved. Furthermore, the current/voltage ripples on the primary-side power ports are reduced due to the interleaving operation. Zero-voltage switching and zero-current switching are realized for the active switches and diodes, respectively. A typical FB-TPC with voltage-doubler rectifier developed by the proposed method is analyzed in detail. Operation principles, control strategy, and characteristics of the FB-TPC are presented. Experiments have been carried out to demonstrate the feasibility and effectiveness of the proposed topology derivation method.

Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs

Abstract: Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.

Negative Capacitance Behavior in a Leaky Ferroelectric

Abstract: We present a simulation study of the negative capacitance effect incorporating leakage through the ferroelectric (FE) negative capacitor. The dynamics of the FE is modeled using the Landau–Khalatnikov equation. When an FE and a dielectric are simply connected in series without a metal contact between them, the stabilization of negative capacitance remains unchanged irrespective of leakage. However, when a metal is used, any finite leakage through the FE makes it impossible to stabilize negative capacitance at the steady state. Nonetheless, when a voltage is applied, the series configuration enters the negative capacitance state and as long as the gate voltage is cycled faster than the time needed by the leakage current to discharge all the capacitors, the transistor shows improved subthreshold swing. These results are expected to provide insight into understanding and analyzing recent experimental results on negative capacitance.

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

Abstract: There is a rising interest in employing the negative capacitance (NC) effect to achieve sub-60 mV/decade (below the thermal limit) switching in field-effect transistors (FETs). The NC effect, which is an effectual amplification of the applied gate potential, is realized by incorporating a ferroelectric material in series with a dielectric in the gate stack of a FET. One of the leading challenges to such NC-FETs is the variable substrate capacitance exhibited in 3D semiconductor channels (bulk, Fin, or nanowire) that minimizes the extent of sub-60 mV/decade switching. In this work, we demonstrate 2D NC-FETs that combine the NC effect with 2D MoS2 channels to extend the steep switching behavior. Using the ferroelectric polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)), these 2D NC-FETs are fabricated by modification of top-gated 2D FETs through the integrated addition of P(VDF-TrFE) into the gate stack. The impact of including an interfacial metal between the ferroelectric and dielectric ...

A Novel SVPWM Algorithm for Five-Level Active Neutral-Point-Clamped Converter

Abstract: The five-level active neutral-point-clamped (5L-ANPC) converter is becoming an attractive topology of multilevel converter family. A novel SVPWM algorithm based on line voltage coordinate was studied in this paper to overcome shortcomings of the traditional algorithm. Through coordinate transformation, steps of determining the basic vectors and the solution about the basic vector corresponding action time are simplified. Combining with the characteristics of 5L-ANPC converter and the new control algorithm, a method of controlling the voltage balancing of dc-link capacitors and floating-capacitors is proposed. According to the voltage of dc-link capacitors, the suitable switching sequence which can balance the voltage of dc-link capacitors is chosen. The high common-mode voltage will affect the service life of motor and reduce the reliability of the system especially in high-voltage converter. The common-mode voltage is also reduced by choosing the right switching state in this paper. The validity of the proposed method was proved by the experimental results.

An Active Cross-Connected Modular Multilevel Converter (AC-MMC) for a Medium-Voltage Motor Drive

Abstract: This paper presents an active cross-connected modular multilevel converter (AC-MMC) based on series-connected half-bridge modules. It is intended for completely enhancing the performance of a medium-voltage motor drive system in the full speed range from standstill to rated speed under all load conditions. The proposed AC-MMC circuit is characterized by the cross connection of upper and lower arm middle taps through a branch of series-connected half-bridge converters, which have an identical voltage and current rating with the submodules in the upper and lower arms. This cross-connected branch provides a physical power transfer channel for the upper and lower arms. By properly controlling the amount of high-frequency current flowing through the cross-connected branch, the power balance between the upper and lower arms is achieved even at a zero/low motor speed under constant torque condition. Meanwhile, no common-mode voltage is introduced in the whole speed range. A control strategy with focus on submodule capacitor voltage control is also proposed in this paper to guarantee the normal converter operation. Simulation results obtained from a 4160-V, 1-MW model verify the feasibility of the proposal. Experiments on a downscaled prototype also confirm the validity of the novel circuit and the associated control strategy.

On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film

Abstract: Internet-of-Things (IoT) technologies require a new energy-efficient transistor which operates at ultralow voltage and ultralow power for sensor node devices employing energy-harvesting techniques as power supply. In this paper, a practical device design guideline for low voltage operation of steep-slope negative-capacitance field-effect-transistors (NCFETs) operating at sub-0.2V supply voltage is investigated regarding operation speed, material requirement and energy efficiency in the case of ferroelectric HfO2 gate insulator, which is the material fully compatible to Complementary Metal-Oxide-Semiconductor(CMOS) process technologies. A physics-based numerical simulator was built to design NCFETs with the use of experimental HfO2material parameters by modeling the ferroelectric gate insulator and FET channel simultaneously. The simulator revealed that NCFETs with ferroelectric HfO2 gate insulator enable hysteresis-free operation by setting appropriate operation point with a few nm thick gate insulator. It also revealed that, if the finite response time of spontaneous polarization of the ferroelectric gate insulator is 10-100psec, 1-10MHz operation speed can be achieved with negligible hysteresis. Finally, by optimizing material parameters and tuning negative capacitance, 2.5 times higher energy efficiency can be achieved by NCFET than by conventional MOSFETs. Thus, NCFET is expected to be a new CMOS technology platform for ultralow power IoT.

Experimental study on polarization-limited operation speed of negative capacitance FET with ferroelectric HfO 2

Abstract: We have experimentally investigated the polarization-limited operation speed of Negative Capacitance FET (NCFET) through direct measurement of negative capacitance in transient behavior of ferroelectric HfO 2 capacitor and physics-based modeling, for the first time. Systematic analysis of frequency dependence and transient characteristics of ferroelectric HfO 2 capacitor enabled accurate parameter extraction. With extracted parameters, our newly developed time-dependent NCFET model provided the evidence that NCFET can operate at >MHz, which is suitable for ultralow power IoT application.

Stabilization of a Cascaded DC Converter System via Adding a Virtual Adaptive Parallel Impedance to the Input of the Load Converter

Abstract: Connecting converters in cascade is a basic configuration of dc distributed power systems (DPS). The impedance interaction between individually designed converters may make the cascaded system become unstable. The previous presented stabilization approaches not only need to know the information of the regulated converter, but also have to know the characteristics of the other converters in the system, which are contradictory to the modularization characteristic of dc DPS. This letter proposes an adaptive-input-impedance-regulation (AIIR) method, which connects an adaptive virtual impedance in parallel with the input impedance of the load converter, to stabilize the cascaded system. This virtual impedance can adaptively regulate its characteristic for different source converters. Therefore, with the AIIR method, all the load converters can be designed to a fixed standard module to stably adapt various source converters. In addition, at any cases, the AIIR approach only changes the load converter's input impedance in a very small frequency range to keep the load converter's original dynamic performance. The requirements on the AIIR method are derived and the control strategies to achieve the AIIR method are proposed. Finally, considering the worst stability problem that often occurs at the system whose source converter is an LC filter, a load converter cascaded with two different LC input filters is fabricated and tested to validate the effectiveness of the proposed AIIR control method.

Compact models of negative-capacitance FinFETs: Lumped and distributed charge models

Abstract: This work presents insights into the device physics and behaviors of ferroelectric based negative capacitance FinFETs (NC-FinFETs) by proposing lumped and distributed compact models for its simulation. NC-FinFET may have a floating metal between ferroelectric (FE) and the dielectric layers and the lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used and at each point in the channel the ferroelectric layer will impact the local channel charge. This distributed effect has important implications on device characteristics as shown in this paper. The proposed compact models have been implemented in circuit simulators for exploring circuits based on NC-FinFET technology.

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Abstract: In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the nonhysteretic operation of NC transistors. We report a clear and significant double improvement in: 1) subthreshold swing and 2) gate overdrive, using the NC effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14-nm node ultrathin body and box fully depleted silicon-on-insulator FET can operate at 0.26 V instead of 0.9 V gate voltage using the NC effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double-gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the NC effect and reduce the ferroelectric’s optimized thickness. A 14-nm node double-gate negative capacitance FET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.

Time-Dependent Negative Capacitance Effects in Al2O3/BaTiO3 Bilayers

Abstract: The negative capacitance (NC) effects in ferroelectric materials have emerged as the possible solution to low-power transistor devices and high-charge-density capacitors Although the steep switching characteristic (subthreshold swing < sub-60 mV/dec) has been demonstrated in various devices combining the conventional transistors with ferroelectric gates, the actual applications of the NC effects are still some way off owing to the inherent hysteresis problem This work reinterpreted the hysteretic properties of the NC effects within the time domain and demonstrated that capacitance (charge) boosting could be achieved without the hysteresis from the Al2O3/BaTiO3 bilayer capacitors through short-pulse charging This work revealed that the hysteresis phenomenon in NC devices originated from the dielectric leakage of the dielectric layer The suppression of charge injection via the dielectric leakage, which usually takes time, inhibits complete ferroelectric polarization switching during a short pulse time

Improved resistive shunt by means of negative capacitance: new circuit, performances and multi-mode control

Abstract: This paper deals with vibration control by means of piezoelectric patches shunted with electrical impedances made up by a resistance and a negative capacitance. The paper analyses most of the possible layouts by which a negative capacitance can be built and shows that a common mathematical description is possible. This allows closed formulations to be found in order to optimise the electrical network for mono- and multi-mode control. General analytical formulations are obtained to estimate the performance of the shunt in terms of vibration reduction. In particular, it is highlighted that the main effect of a negative capacitance is to artificially enhance the electromechanical coupling factor, which is the basis of performance estimation. Stability issues relating to the use of negative capacitances are especially addressed using refined models for the piezoelectric patch capacitance. Furthermore, a new circuit based on a couple of negative capacitances is proposed and tested, showing better performances than those provided by the usual layouts with a single negative capacitance. Finally, guidelines and analytical formulations to deal with the practical implementation of negative capacitance circuits are provided.

An Interleaved Half-Bridge Three-Port Converter With Enhanced Power Transfer Capability Using Three-Leg Rectifier for Renewable Energy Applications

Abstract: In this paper, an interleaved half-bridge (IHB) three-port converter (TPC) is proposed for a renewable power system. The IHB-TPC is used to interface three power ports: 1) one source port; 2) one battery port; and 3) one isolated load port. The proposed IHB-TPC is derived by integrating two half-bridge TPC modules. A parallel configuration is adopted for the primary side of the two half-bridge modules, while a parallel–series configuration is adopted for the secondary side of the two modules. The power can be transferred from the source and the battery to the load within the whole switching cycle with the proposed IHB-TPC. It means there are no additional conduction losses caused by the circulating current or the free-wheeling operation stage. Hence, the voltage gain can be extended, and the output filter can be reduced. Zero-voltage switching is realized for all the four main switches to reduce the switching losses. Two of the three ports can be tightly regulated by adopting pulsewidth modulation plus phase-shift control, while the third port is left unregulated to maintain power balance for the system. The operation principles and the performances of the proposed converter are analyzed in detail. The experimental results are given to verify the feasibility and the effectiveness of the proposed converter.

Stabilization of Cascaded DC/DC Converters via Adaptive Series-Virtual-Impedance Control of the Load Converter

Abstract: It has been shown recently that a cascaded dc/dc converter system can be stabilized via amplitude compensation (SAC) or phase compensation (SPC) for the input impedance of the load converter. In this letter, it is shown that the cascaded system when adopting the SAC is unconditionally stable but conditionally stable when adopting the SPC, that is, SAC is more stable than SPC. Then, the comparison is carried out for the parallel-virtual-impedance (PVI) and series-virtual-impedance (SVI) control strategies that are adopted to implement the SAC, and it is found that only the SVI control strategy can achieve the SAC for the whole load and input voltage range of the load converter without limitation. Therefore, SVI is in general better than PVI when realizing SAC. Following on this, an adaptive mechanism is introduced to improve the traditional SVI control strategy so that the load converter can be stably connected to different source converters such as $LC$ input filters and traditional dc/dc converters. Finally, a load converter cascaded with three different source converters is fabricated to validate the effectiveness of the proposed adaptive SVI control strategy.

Switching Frequency Stabilization Techniques for Adaptive On-Time Controlled Buck Converter With Adaptive Voltage Positioning Mechanism

Abstract: Unpredictable continuous conduction mode switching frequency variation that occurs commonly in ripple-based control can lead to serious electronic–magnetic interface noise problems and thus increase the effort required for designing noise filters. Sensorless load current correction and dynamic tolerance window techniques are proposed in this paper to reduce the frequency variations caused by conduction losses without employing complicated circuits such as phase-locked loop or current sensors. The proposed dc–dc buck converter with input voltage ranging from 2.7 to 3.6 V and an output voltage between 1.0 and 1.2 V was fabricated using a standard 0.18-μm CMOS process, and the converter achieved excellent adaptive voltage positioning function. Experimental results show that the switching frequency variation improved approximately 60% over traditional techniques in constant on-time control when the load current was changed from 150 to 1000 mA. The measurement results also show that frequency variation across the entire input/output and loading ranges was lowered to only ±2.6%. The maximum power efficiency was 88.2% at 150 mA with an input voltage of 2.7 V.

Equivalent circuit modeling of LLC resonant converter

Abstract: LLC resonant converter is widely used in industry. However, up to now, no simple and accurate small-signal equivalent circuit model is available. This paper proposes an equivalent circuit model of LLC resonant converter. The simple equivalent circuit model is derived based on modification and simplification of extended describing function method. The model can well predicts the small-signal behaviors observed in LLC resonant converter, whenever switching frequency is below, close to or above the resonant frequency. For the first time, analytical expressions for control to output voltage, input to output voltage, input impedance and output impedance are provided to aid close loop feedback design. Simplis simulation and experimental results are presented to prove the accuracy of the model.

Negative capacitance transistors with monolayer black phosphorus

Abstract: Quantum transport properties of negative capacitance transistors (NC-FETs) with monolayer black phosphorus (ML-BP) are theoretically studied. Our calculations show that atomistic thin ML-BP can enhance the amplification effect of the ferroelectric layer, and subthreshold swing is effectively reduced to 27 mV per decade in ML-BP NC-FETs. Device performance can be further improved by increasing the thickness of ferroelectric layer and using thinner or high-k insulate layer. Due to the temperature dependence of ferroelectric layer ML-BP NC-FETs have higher on-state current at low temperature, which is different from that of MOSFETs. By considering the metal–ferroelectric interface layer, our calculations show that the device performance is degraded by the interface. Compared with the International Technology Roadmap (ITRS) 2013 requirements, ML-BP NC-FETs can fulfil the ITRS requirements for high-performance logic with a reduced supply voltage. The new device can achieve very low power delay product per device width at VD=0.3 V, which is just 44% of that in ML-BP FETs. Two-dimensional materials can improve the performance of a novel class of low-power transistors, predict scientists. Yan Zhou at Nanjing University and co-workers in China and Canada aimed to clarify the properties of negative capacitance field-effect transistors (NC-FETs), which have recently been proposed as a method for increasing voltage amplification while using much less power than conventional devices. In NC-FETs, a voltage applied to two metallic layers electrically polarizes an intermediate layer. Using a ferroelectric as a spacer leads to an effect called negative capacitance, which provides voltage amplification in a way that is fundamentally different from traditional transistors. Zhou’s team simulated the performance of a NC-FET that, by introducing a single atomic layer of black phosphorus, further improves the amplification effect. The proposed system is expected to be useful in the design of low-power circuits.

Impedance Control Network Resonant DC–DC Converter for Wide-Range High-Efficiency Operation

Abstract: This paper introduces a new resonant converter architecture that utilizes multiple inverters and a lossless impedance control network (ICN) to maintain zero-voltage switching and near zero-current switching across wide operating ranges. Hence, the ICN converter is able to operate at fixed frequency and maintain high efficiency across wide ranges in input and output voltages and output power. The ICN converter architecture enables increase in switching frequency (hence reducing size and mass), while achieving very high efficiency. Three prototype 200-W 500-kHz ICN resonant converters, one with low-Q, one with medium-Q, and one with high-Q resonant tanks, designed to operate over an input voltage range of 25 to 40 V and an output voltage range of 250 to 400 V are built and tested. The low-Q prototype ICN converter achieves a peak efficiency of 97.1%, maintains greater than 96.4% full power efficiency at 250 V output voltage across the nearly 2:1 input voltage range, and maintains full power efficiency above 95% across its full input and output voltage range. It also maintains efficiency above 94.6% over a 10:1 output power range across its full input and output voltage range owing to the use of burst-mode control.

Alternative interpretations for decreasing voltage with increasing charge in ferroelectric capacitors

Abstract: Recent claim on the direct observation of a negative capacitance (NC) effect from a single layer epitaxial Pb(Zr0.2,Ti0.8)O3 (PZT) thin film was carefully reexamined, and alternative interpretations that can explain the experimental results without invoking the NC effect are provided. Any actual ferroelectric capacitor has an interfacial layer, and experiment always measures the sum of voltages across the interface layer and the ferroelectric layer. The main observation of decreasing ferroelectric capacitor voltage (VF) for increasing ferroelectric capacitor charge (QF), claimed to be the direct evidence for the NC effect, could be alternatively interpreted by either the sudden increase in the positive capacitance of a ferroelectric capacitor or decrease in the voltage across the interfacial layer due to resistance degradation. The experimental time-transient VF and QF could be precisely simulated by these alternative models that fundamentally assumes the reverse domain nucleation and growth. Supplementary experiments using an epitaxial BaTiO3 film supported this claim. This, however, does not necessarily mean that the realization of the NC effect within the ferroelectric layer is impractical under appropriate conditions. Rather, the circuit suggested by Khan et al. may not be useful to observe the NC effect directly.

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors

Abstract: Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications. The unique feature which makes these devices suitable for ultra-low voltage operation is the steep slope achieved by negative capacitance of the ferroelectric oxide based gate stack. This property is being actively explored to overcome the fundamental 60 mV/decade sub threshold swing limit associated with conventional MOSFETs. In this paper, we focus on the circuit implications of the steep slope behavior of the FEFETs. We analyze the characteristics of FEFETs to get insights into their performance, and show both higher ON current and higher gate capacitance compared to standard transistors. We design and simulate a ring oscillator and a Kogge Stone adder using FEFET devices and evaluate the impact of ferroelectric layer thickness on the performance. Our analysis shows that FEFET based circuits consume lower energy compared to CMOS circuits at VDD

Revisiting the Theory of Ferroelectric Negative Capacitance

Abstract: In this paper, we revisit the theory of negative capacitance in: 1) a standalone ferroelectric; 2) a ferroelectric–dielectric; and 3) a ferroelectric–semiconductor series combination, and show that it is important to minimize the total Gibbs free energy of the combined system (and not just the free energy of the ferroelectric) to obtain the correct states. The theory is explained both analytically and using numerical simulation, for ferroelectric materials with the first-order and second-order phase transitions. The exact conditions for different regimes of operation in terms of hysteresis and gain are derived for ferroelectric–dielectric combination. Finally, the ferroelectric–semiconductor series combination is analyzed to gain insights into the possibility of realization of steep slope transistors in a hysteresis-free manner.