Showing papers on "p–n junction published in 1998"

High-voltage accumulation-layer UMOSFET's in 4H-SiC

Abstract: A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 /spl mu/m drift region), a specific on-resistance of 15.7 m/spl Omega/-cm/sup 2/ at room temperature, and a gate oxide field of 3 MV/cm.

High-performance GaN p-n junction photodetectors for solar ultraviolet applications

Abstract: The fabrication and characterization of ultraviolet photodetectors based on GaN p-n junctions is reported. The devices are grown by metalorganic vapour phase epitaxy on basal-plane sapphire substrates. These detectors are visible-blind with a sharp wavelength cut-off at 360 nm. The photocurrent is linear with incident power from up to , with a responsivity of at 360 nm. The device time response is dominated by the effective resistance-capacitance time constant, and a 105 ns response is estimated for very low load resistances. A comparison with the response of GaN photoconductor detectors is also presented. The application of these high-performance photodetectors for solar ultraviolet monitoring is described.

Scanning capacitance spectroscopy: An analytical technique for pn-junction delineation in Si devices

Abstract: Scanning capacitance spectroscopy (SCS), a variant of scanning capacitance microscopy (SCM), is presented. By cycling the applied dc bias voltage between the tip and sample on successive scan lines, several points of the high-frequency capacitance–voltage characteristic C(V) of the metal–oxide–semiconductor capacitor formed by the tip and oxidized Si surface are sampled throughout an entire image. By numerically integrating dC/dV, spatially resolved C(V) curves are obtained. Physical interpretation of the C(V) curves is simpler than for a dC/dV image as in a single-voltage SCM image, so that the pn junction may be unambiguously localized inside a narrow and well-defined region. We show SCS data of a transistor in which the pn junction is delineated with a spatial resolution of ±30 nm. This observation is consistent with the conclusion that SCS can delineate the pn junction to a precision comparable to the Si depletion width, in other words, the actual size of the electrical pn junction. A physical model to explain the observed SCS data near the pn junction is presented.

Origin of conductivity and low-frequency noise in reverse-biased GaN p-n junction

Abstract: We study the origins of conductivity and low-frequency noise in GaN p-n junctions under reverse bias. Carrier hopping through defect states in the space charge region is identified as the main mechanism responsible for low bias conductivity. Threading dislocations appear the most likely source of such defect states. At higher bias hopping is supplemented with Poole–Frenkel emission. A relatively high level of 1/f-like noise is observed in the diode current. The bias and temperature dependencies of the noise current are investigated.

Optoelectronic semiconductor diodes and devices comprising same

Abstract: An optoelectronic semiconductor diode is made from a layer of many small individual particles (2) containing doping junctions (10) positioned between two contact surfaces (6, 8) mechanically supported by substrates (4). In the preferred embodiment, the particles are formed of a semiconductor, such as indium gallium nitride, as the active region. The particles are of a size on the order of 10 to 100 microns and are formed by reacting metallic gallium and indium with ammonia, or by a similar method. Electrical contacts are made to the particles (2) by conductive films (6, 8) that have been deposited on the inner surfaces of the substrates (4). These contacts can be either reflective or transparent. The particles (2) each contain a p-n or similar junction (10), created either by diffusing in dopants or by selectively activating dopants that are already present. When a forward bias is applied to a so formed LED, minority carriers spill over the junction (10) and recombine with majority carriers, thus producing light. Powder LEDs according to the present invention can in principle be manufactured to operate on any wavelength within the visible spectrum.

Method for producing a pn-junction for a semiconductor device of SiC

Abstract: A method for producing a pn-junction for a semiconductor device of SiC intended to have at least one lateral zone of junction termination with a lower doping concentration of a first conductivity type than a main zone for smearing out the electrical field at said junction comprising at least the step of applying a first layer of SiC over the entire surface and on top of a second layer of SiC. A mask is applied on the first layer over a portion thereof where said main zone and an ohmic contact are to be formed. It is after that etched through the first layer to the second layer while leaving a main zone of said first layer and a contact layer thereof under said mask.

Electronic device, in particular for switching electric currents, for high reverse voltages and with low on-state losses

Abstract: A p-n junction is connected between two terminals. The p-n junction is formed between two semiconductor regions of a semiconductor with a breakdown field strength of at least 106 V/cm. A channel region, which adjoins the p-n junction is connected in series with a silicon component between the two terminals. The channel region is provided in a first of the two semiconductor regions. A depletion zone of the p-n junction carries the reverse voltage in the off state of the silicon component. The silicon component is preferably a

Al + and B + implantations into 6H-SiC epilayers and application to pn junction diodes

Abstract: Aluminum (Al) and boron (B) ion implantations at room temperature into n-type 6H-SiC epilayers have been investigated. Rutherford backscattering spectroscopy (RBS) channeling measurements revealed larger lattice damage in Al+ implantation at a given total implantation dose. A nearly perfect electrical activation ratio (>90%) could be attained by high-temperature annealing at 1600°C for Al+ and 1700°C for B+ implantations. Mesa pn junction diodes formed by either Al+ or B+ implantation with a 1×1014 cm−2 dose exhibited high blocking voltages of 950∼1070 V, which are 80∼90% of the ideal value predicted for the diode structure. The forward current can clearly be divided into two components of diffusion and recombination currents. B+-implanted diodes showed higher breakdown voltage on average but poor forward conduction. Comparison of the performance of Al+ and B+-implanted diodes is discussed.

Photodiode arrays having minimized cross-talk between diodes

Abstract: Photodiode arrays are formed with close diode-to-diode spacing and minimized cross-talk between diodes in the array by isolating the diodes from one another with trenches that are formed between the photodiodes in the array. The photodiodes are formed of spaced regions in a base layer, each spaced region having an impurity type opposite to that of the base layer to define a p-n junction between the spaced regions and the base layer. The base layer meets a substrate at a boundary, with the substrate being much more heavily doped than the base layer with the same impurity type. The trenches extend through the base layer and preferably into the substrate. Minority carriers generated by absorption of light photons in the base layer can only migrate to an adjacent photodiode through the substrate. The lifetime and the corresponding diffusion length of the minority carriers in the substrate is very short so that all minority carriers recombine in the substrate before reaching an adjacent photodiode.

Sputtered Cr and Reactively Sputtered CrN x Serving as Barrier Layers Against Copper Diffusion

Abstract: The barrier capability of sputter deposited Cr and reactively sputter deposited CrN x films against Cu diffusion in a structure of Cu/barrier/p n junction diodes was investigated by means of thermal annealing at elevated temperatures in conjunction with electrical measurements and material analysis. For a 500 A thick barrier layer, the barrier capability of a pure Cr layer was limited to temperatures up to 500°C, while CrN x films sputter deposite in a gas mixture of Ar and N 2 showed improved barrier capabilities. With Ar/N 2 flow rates of 24/6 to 24/12 standard cubic centimeters per minute, the deposited CrN x films possessed a much improved barrier capability. In particular, the Cu/CrN x (24/9)/p - n junction diodes were capable of sustaining 30 min of t ermal anneal at temperatures up to 700°C without degradation of the diodes' electrical characteristics. The failure of Cu/Cr/p + n and Cu/CrN x /p + n junction diodes under extreme thermal treatment was presumed to arise from two mechanisms: grain boundary diffusion for lightly nitrogen doped CrN x and pure Cr barriers, and localized defect (microcrack) diffusion for excessively nitrogen doped CrN x barriers.

A light-emitting device using a lateral junction grown by molecular beam epitaxy on GaAs (311)A-oriented substrates

Abstract: A lateral p–n junction allows direct injection of electrons and holes in the active layer of devices such as laser diodes and can reduce carrier relaxation time and increase modulation bandwidth. Light-emitting diodes were made on patterned GaAs (311)A-oriented substrates by using a lateral p–n junction formed in GaAs–silicon-doped epilayers grown by molecular beam epitaxy. Good electroluminescence at room temperature was obtained for both GaAs single layers and GaAs/AlGaAs multiple quantum well structures.

Perimeter governed minority carrier lifetimes in 4H-SiC p + n diodes measured by reverse recovery switching transient analysis

Abstract: Minority carrier lifetimes in epitaxial 4H-SiC p+n junction diodes were measured via an analysis of reverse recovery switching characteristics. Behavior of reverse recovery storage time (ts) as a function of initial ON-state forward current (IF) and OFF-state reverse current (IR) followed well-documented trends which have been observed for decades in silicon p+n rectifiers. Average minority carrier (hole) lifetimes (τp) calculated from plots of ts vs IR/IF strongly decreased with decreasing device area. Bulk and perimeter components of average hole lifetimes were separated by plotting 1/τp as a function of device perimeter-to-area ratio (P/A). This plot reveals that perimeter recombination is dominant in these devices, whose areas are all less than 1 mm2. The bulk minority carrier (hole) lifetime extracted from the 1/τp vs P/A plot is approximately 0.7 µs, well above the 60 ns to 300 ns average lifetimes obtained when perimeter recombination effects are ignored in the analysis. Given the fact that there has been little previous investigation of bipolar diode and transistor performance as a function of perimeter-to-area ratio, this work raises the possibility that perimeter recombination may be partly responsible for poor effective minority carrier lifetimes and limited performance obtained in many previous SiC bipolar junction devices.

Investigation of the Leakage Current in GaN P-N Junctions

Abstract: We report on the fabrication and evaluation of leakage current based on GaN p-n junctions grown by metalorganic vapor phase epitaxy over sapphire. Si and Mg were used as n- and p-type dopants, respectively. Reactive ion etching was used to define mesas of different sizes and metal ohmic contacts were fabricated. Reverse dark current of 15 pA/mm2 was measured under -8 V bias at room temperature, and that of 900 pA/mm2 was measured under -5 V bias at 480 K. Surface leakage along the mesa sidewalls is suggested to be the main source of leakage under a low bias voltage, and tunneling effects appear to be the main reason for junction breakdown.

Ultra-shallow P+/N junctions formed by recoil implantation

Abstract: The concept of recoil implantation is proposed to facilitate fabrication of ultrashallow p+/n junctions. In this method, a thin boron film is first deposited onto the Si wafer surface. Then the boron atoms are knocked into the Si substrate by Ge implantation or Ar plasma source ion implantation. Dopant activation and damage removal are achieved via rapid thermal annealing. Preliminary results show the realization of sub-100 nm deep p+/n junctions with this technique. Monte Carlo simulations were performed to predict the recoiled boron profiles, and agree well with the experimental results.

MOS device structure and method for reducing PN junction leakage

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

A Two-Step Low-Temperature Process For A P-N Junction Formation Due To Hydrogen Enhanced Thermal Donor Formation In P-Type Czochralski Silicon

Abstract: The incorporation of hydrogen into standard p-type Czochralski (Cz) silicon (≥1 Ωcm) by a 110 MHz plasma treatment at 260°C leads to the formation of an n-type region due to hydrogen enhanced thermal donor (TD) formation in hydrogenated regions of the wafer, if a subsequent annealing in air is applied at 450°C. Spreading resistance probe (SRP) and light beam induced current (LBIC) measurements were used for the experimental analysis. The p-n junction depth, i. e. the counter doping by TDs, depends on the initial doping level of the p-type substrate, and therefore on the post-hydrogenation annealing time. The penetration of the n-type region into the wafer bulk is driven by a rapid hydrogen diffusion. The essential process for a TD generation is the creation of metastable hydrogen molecular species around 260°C and their decay at 450°C.

Optical arrangement for balancing the beam of one or more high power diode lasers arranged one above another

Abstract: An optical arrangement is provided for balancing the beam of one or more high-power diode lasers (HP-DL) arranged one above another. The beam, which is known to diverge very differently in the direction of the pn junction and perpendicular to the pn junction of the emitters of an HP-DL arranged in a row is imaged at a point with high power density and high beam quality the arrangement. Present for this purpose are optical devices which spread out the radiation in a mutually offset fashion in the direction of the pn junction while the radiation is superimposed perpendicular to the pn junction.

Semi-conductor device protected by electrostatic protection device from electrostatic discharge damage

Abstract: A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.

Anomalous temperature dependence of erbium-related electroluminescence in reverse biased silicon p-n junction

Abstract: Electroluminescence (EL) and electrophysical characteristics of erbium and oxygen coimplanted and annealed p–n junctions, characterized by higher values of the Er3+-related EL intensity at ∼1.54 μm in the breakdown regime at 300 K as compared with that at 85 K, have been studied in the temperature range from 85 to 300 K. Hole traps in the Er–O codoped n layer were found to be responsible for the anomalous EL behavior. Er-related EL was observed in the same samples in avalanche breakdown at high temperatures and in tunnel breakdown at low temperatures.

Accurate extraction of the diffusion current in silicon p-n junction diodes

Abstract: An accurate method for the extraction of the reverse diffusion current component in a silicon p-n junction diode is proposed. It combines capacitance–voltage and current–voltage measurements on an array of diodes with different geometry in order to separate the peripheral and the volume leakage current components. The corrected volume capacitance is then used to calculate the depletion width as a function of the reverse bias. Extrapolation of the reverse current to zero depletion width results in the diffusion current part, both for the volume and for the peripheral component. From the temperature dependence, a thermal activation energy of 1.12 eV is obtained. The volume diffusion current density of the p-type Czochralski wafers studied, shows a pronounced substrate dependence, while the peripheral diffusion current density is constant. Finally, the implications for the extraction of the effective bulk recombination lifetime are discussed.

Characterization of phosphorus doped n-type 6H-silicon carbide epitaxial layers produced by nuclear transmutation doping

Abstract: Aluminum doped 6H-SiC epitaxial layers (p-type net doping: NA−ND=5.2×1015 cm−3, thickness 3 μm) on a p+ doped 6H-SiC substrate (NA−ND=1018 cm−3) were irradiated with neutrons in a nuclear reactor. The neutron fluences applied were 9.4×1019, 3.5×1020, and 6.4×1020 cm−2. The phosphorus impurity in SiC is produced by a nuclear (n,γ) reaction with the decay of 31Si to 31P. The irradiated samples were subsequently annealed at temperatures between 800 and 1850 °C. The annealing behavior was studied by low temperature photoluminescence, Fourier transform infrared spectroscopy, and Hall effect and I–V and C–V measurements. After the annealing process the 6H-SiC p-type epilayer changed to n type resulting in a pn junction within the material. The properties of the pn junction were characterized.

P—N Junction

Abstract: Most semiconductor devices contain at least one junction between p-type and n-type material. P—n junction theory serves as the foundation of the physics of semiconductor devices. The basic theory of current—voltage characteristics of p—n junctions was established by Shockley (1949). This theory was then expanded by Sah et al. (1957) and Moll (1958).

Semiconductor device having a monotonically decreasing impurity concentration

Abstract: An n- layer (2E) having a low impurity concentration is epitaxially grown on a surface (S1) of an n+ silicon substrate (1) having a high impurity concentration to a depth (D), and phosphorus ions (P) are implanted from the surface (S1) to the inside of the n- layer (2E). A SiO2 film is formed on the surface S1 by thermal oxidation, and an opening hole is formed in the SiO2 film. Using the opening hole, p-type impurities are implanted and diffused by thermal oxidation in the ion-implanted n- layer (2E), forming a p-type diffusion layer (well) from the surface (S1) to a predetermined depth. In this way, an n layer is formed in place of the n- layer (2E). The concentration distribution of impurity in the n layer monotonically decreases from the side of the surface (S1) and reaches its minimum on the side of an interface (BS). Then, a predetermined electrode is formed, completing the device. Thus, variations in both on-state resistance and breakdown voltage are reduced in a semiconductor device having a pn junction.

Semiconductor device with a tunnel diode and method of manufacturing same

Abstract: A semiconductor device with a tunnel diode (23) is particularly suitable for various applications. Such a device comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types and having doping concentrations which are so high that breakdown between them leads to conduction by means of tunnelling. A disadvantage of the known device is that the current-voltage characteristic is not yet steep enough for some applications. In a device according to the invention, the portions (2A, 3A) of the semiconductor regions (2, 3) adjoining the junction (23) comprise a mixed crystal of silicon and germanium. It is surprisingly found that the doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions (2, 3). The tunnelling efficiency is substantially improved as a result of this, and also because of the reduced bandgap of said portions (2A, 3A), and the device according to the invention has a much steeper current-voltage characteristic both in the forward and in the reverse direction. This opens perspectives for inter alia an attractive application where the tunnelling pn junction (23) is used as a transition between two conventional diodes, for example pn or pin diodes, which are used one stacked on the other and which can be formed in a single epitaxial growing process thanks to the invention. The portions (2A, 3A) adjoining the tunnelling junction (22) are preferably 5 to 30 nm thick and comprise between 10 and 50 at % germanium. The doping concentration may be 6×1019 or even more than 1020 at/cm3. The invention further relates to a simple method of manufacturing a device according to the invention. This is preferably done at a temperature of between 550° C. and 800° C.

Extension of the impedance field method to the noise analysis of a semiconductor junction: Analytical approach

Abstract: We present an analytical procedure to perform the local noise analysis of a semiconductor junction when both the drift and diffusive parts of the current are important. The method takes into account space-inhomogeneous and hot-carriers conditions in the framework of the drift-diffusion model, and it can be effectively applied to the local noise analysis of different devices: n+nn+ diodes, Schottky barrier diodes, field-effect transistors, etc., operating under strongly inhomogeneous distributions of the electric field and charge concentration.

p-n junction peripheral current analysis using gated diode measurements

Abstract: A modified method for analysis of the current–voltage characteristics of a gated diode structure is proposed and validated in order to investigate the peripheral reverse current in a silicon p-n junction diode. The peripheral generation current in modern p-n diodes is attributed fully to surface generation underneath the thick field oxide surrounding the structure, which typically contains a high density of interface traps. For a gated diode structure, the current region observed for large gate voltages, VG, is linked to the generation associated with the depletion at the Si-thick SiO2 interface. It will be shown that, compared to the classical analysis, this current step is a better alternative to assess the peripheral generation. The 25 times higher sensitivity of gated diode measurements in this mode allows one to reduce the test device perimeter and dimensions, without penalizing the measurement resolution for interface states. The main advantage of the proposed method is related to the fact that for ...