Showing papers on "Silicon on insulator published in 2002"

Multiple-gate SOI MOSFETs: device design guidelines

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

Abstract: The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

SOI technology for the GHz era

Abstract: Silicon-on-insulator (SOI) CMOS offers a 20–35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-µm generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-µm generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-µm generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

Three-dimensional integrated semiconductor devices

Abstract: The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.

Method of forming a transistor with a strained channel

Abstract: A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.

Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

Abstract: We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for the first time that the processes required for stacking active device layers preserve the intrinsic electrical characteristics of state-of-the-art short-channel MOSFETs and ring oscillator circuits, which is critical to the success of high performance 3D ICs.

Observation of Raman emission in silicon waveguides at 1.54 μm

Abstract: We report the first measurements of spontaneous Raman scattering from silicon waveguides Using a 143 m pump, both forward and backward scattering were measured at 154 m from Silicon-On-Insulator (SOI) waveguides From the dependence of the Stokes power vs pump power, we extract a value of (41 +/- 25) x 10-7 cm-1 Sr-1 for the Raman scattering efficiency The results suggest that a silicon optical amplifier is within reach The strong optical confinement in silicon waveguides is an attractive property as it lowers the pump power required for the onset of Raman scattering The SiGe material system is also discussed

Method of forming an N channel and P channel finfet device on the same semiconductor substrate

Abstract: A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

Finfet CMOS with NVRAM capability

Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM capability arises from the presence of double floating gates arranged on and insulated from a semiconductor fin body, and a control gate arranged on and insulated from the double floating gates. The fabrication of the present device may be accomplished by: providing an SOI wafer and defining a fin on the SOI wafer, the fin may be capped with an insulator layer; providing gate insulator on at least one vertical surface of the FIN; depositing floating gate material over the gate insulator; depositing insulator material on the floating gate material to form the floating gate isolation; depositing control gate material over the isolated floating gate material; removing a portion of the control gate material to expose source and drain regions of the Fin, implanting the Fin to form source/drain regions in the exposed regions of the Fin, and providing insulator material on the Fin. In addition, the NVRAM FinFET allows for horizontal current flow.

Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture

Abstract: Lateral field penetration in the buried oxide (BOX) and underlying substrate of fully depleted SOI MOSFETs is responsible for a dramatic increase of short-channel effects. An original compact model of the latter phenomena is proposed and used to explore optimized architectures of sub-100 nm transistors. Various architectures including the ground-plane MOSFET, are compared using a quasi-2D analysis in order to evaluate the contribution of the BOX to short-channel effects.

Low Temperature Electronics: Physics, Devices, Circuits, and Applications

Abstract: 1. Physics of Silicon at Cryogenic Temperatures 2. Silicon Devices and Circuits 3. Reliability Aspects of Cryogenic Silicon Technologies 4. Radiation Effects and Low-Frequency Noise in Silicon Technologies 5. Heterostructure and Compound Semiconductor Devices 6. Compound Heterostructure Semiconductor Lasers and Photodetectors 7. High-Temperature Superconductors/Semiconductor Hybrid Microwave Devices and Circuits 8. Cryocooling and Thermal Management 9. Applications, Trends, and Perspectives Index

Light propagation characteristics of straight single-line-defect waveguides in photonic crystal slabs fabricated into a silicon-on-insulator substrate

Abstract: Straight single-line defect optical waveguides in photonic crystal slabs are designed by the finite difference time-domain method and fabricated into a silicon-on-insulator (SOI) wafer. By employing an airbridge structure, clear light propagation for both polarizations is observed without any leakage along the waveguide. This experimental result is well explained by photonic bands of pure guided modes. Minimum propagation loss is estimated to be 11 dB/mm. This value is lower than that reported so far for three-line-defect waveguides with an SOI slab structure and almost comparable to that for an index confinement waveguide with a rectangular Si core. This propagation loss is dominated by the scattering loss by some irregularities. However, photonic crystal waveguides have the possibility of an essential lower scattering loss than in the index confinement waveguide because of the inhibition of radiation modes by the photonic bandgap.

FinFET device incorporating strained silicon in the channel region

Abstract: A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

SOI hybrid structure with selective epitaxial growth of silicon

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

DRAM cell with high integration density, and associated method

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

A scanning micromirror with angular comb drive actuation

Abstract: Describes a single crystal silicon, 1/spl times/1 mm/sup 2/, scanning micromirror, which incorporates a novel angular vertical comb drive actuator. Results from our model for the angular vertical comb show that a 50% higher scan angle can be achieved when compared to a staggered vertical comb of equivalent dimensions. The simplified, cost effective, silicon on insulator micro-electromechanical systems, (SOI MEMS), process features self-alignment of the fixed and moving teeth and is fabricated on a single SOI wafer. Static deflection for our fabricated device fits well with the model and a resonant mode optical scan angle of /spl plusmn/18/spl deg/ at 1.4 kHz has been measured.

Impact of the channel thickness on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors

Abstract: We present quantum simulations of single-gated Schottky barrier metal–oxide–semiconductor field-effect transistors on ultrathin silicon on insulator. The electrostatics of such devices is investigated and the influence of the silicon thickness on the Schottky barriers at the source and drain and, thus, the influence on the current–voltage characteristics are elaborated. We show that decreasing the channel layer thickness leads to a strong reduction of the Schottky barrier thickness and thus to an increased gate control of the drain current. The use of ultrathin channel layers improves the off- as well as the on state of such transistors and results in electrical characteristics comparable with conventional metal–oxide–semiconductor field-effect transistors.

Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same

Abstract: A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

High-speed resonant-cavity-enhanced silicon photodetectors on reflecting silicon-on-insulator substrates

Abstract: We report a resonant-cavity-enhanced Si photodetector fabricated on a reflecting silicon-on-insulator (SOI) substrate. The substrate incorporates a two period distributed Bragg reflector (DBR) fabricated using a commercially available double-SOI process. The buried DBR provides a 90% reflecting surface. The resonant-cavity-enhanced Si photodetectors have 40% quantum efficiency at 860 nm and response time of 29 ps. These devices are suitable for 10-Gb/s data communications.

Strained silicon MOSFET having silicon source/drain regions and method for its fabrication

Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon germanium are reduced

Low-loss silicon-on-insulator photonic crystal waveguides

Abstract: Silicon-on-insulator-based 2D photonic crystal waveguides have been optically characterised. The measured total insertion loss is below 19 dB in the waveguides with unpolarised light. With the length mask technique, it is found that the photonic crystal waveguides show propagation losses below 4 dB/mm.

Ultracompact corner-mirrors and T-branches in silicon-on-insulator

Abstract: In this letter, we have designed and fabricated low-loss ultrasmall corner mirrors and T-branches on thin silicon-on-insulator material system. The measured performance of the devices agrees with simulations using finite-difference time-domain calculations. These devices demonstrate the potential of this high-refractive-index-contrast material system for high-density planar optical integrated circuits.

Principles of transient charge pumping on partially depleted SOI MOSFETs

Abstract: A new method to determine the interface trap density in partially depleted silicon-on-insulator (SOI) floating body MOSFETs is proposed for the first time. It can be considered as a "transient" charge-pumping (CP) technique in contrast to the normally used "steady-state" method. In our technique, majority carriers are removed from the floating body by applying a burst of pulses to the transistor gate. The change in the linear drain current after each pulse is used to determine the device interface trap density. The unique advantage of this method is the possibility to use it to characterize SOI MOSFETs without a body contact. The technique proposed is simple, reliable, and can be used for the characterization of deep submicron devices.

Silicon-on-insulator diodes and ESD protection circuits

Abstract: A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and then also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And, the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

Silicon substrates with buried distributed Bragg reflectors for resonant cavity-enhanced optoelectronics

Abstract: We report on a commercially reproducible silicon wafer with a high-reflectance buried distributed Bragg reflector (DBR). The substrate consists of a two-period DBR fabricated using a double silicon-on-insulator (SOI) process. The buried DBR provides a 90% reflecting surface. We have fabricated resonant cavity-enhanced Si photodetectors with 40% quantum efficiency at 860 nm and a full-width at half-maximum of 29 ps suitable for 10 Gbps data communications. We have also implemented double-SOI substrates with 90% reflectivity covering 1300 and 1550 nm for use in Si-based optoelectronics.

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Abstract: Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.

Linearity and low-noise performance of SOI MOSFETs for RF applications

Abstract: The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-/spl rho/ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 /spl mu/m FD-SOI low-noise amplifier (LNA) on high-/spl rho/ SOI substrate obtained the lowest noise figure for applications in the L and S-bands.

Semiconductor device having one of patterned SOI and SON structure

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication

Abstract: A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

Method of manufacturing SOI element having body contact

Abstract: A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.