Showing papers on "Strained silicon published in 2007"

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Method for forming strained silicon nitride films and a device containing such films

Abstract: A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the silicon precursor with a second reactivity characteristic such that a property of the silicon nitride film formed on the substrate changes to provide the strained silicon nitride film.

Forming a type i heterostructure in a group iv semiconductor

Abstract: In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si 1-x Ge x ), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si 1-y Ge y (C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si 1-z Ge z (C). Other embodiments are described and claimed.

Non-volatile solid state resistive switching devices

Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.

Elastically strain-sharing nanomembranes: flexible and transferable strained silicon and silicon?germanium alloys

Abstract: The emerging field of strained-Si based nanomembranes is reviewed, including fabrication techniques, strain-induced band structure engineering, electronic applications and three-dimensional membrane architectures. Elastic strain sharing between thin heteroepitaxial Si and SiGe films, enabled by techniques that allow release of these films from a handling substrate, creates a new material: freestanding, single-crystal, strained nanomembranes. These flexible nanomembranes are virtually dislocation-free and have many potential new applications. Strain engineering also provides opportunities for massively parallel self-assembly of a wide variety of three-dimensional nanostructures.

Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride

Abstract: In the present invention a metal oxide or nitride compound which is a wide-i band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heteroj unction. This p-n heteroj unction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer (118), while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region (4), an intrinsic silicon region (6), and a nickel oxide layer (118) serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monc-lithic three dimensional memory array.

Valley splitting in strained silicon quantum wells modeled with 2° miscuts, step disorder, and alloy disorder

Abstract: Valley splitting (VS) in strained SiGe∕Si∕SiGe quantum wells grown on (001) and 2° miscut substrates is computed in a magnetic field. Calculations of flat structures significantly overestimate, while calculations of perfectly ordered structures underestimate experimentally observed VS. Step disorder and confinement alloy disorder raise the VS to the experimentally observed levels. Atomistic alloy disorder is identified as the critical physics, which cannot be modeled with analytical effective mass theory. NEMO-3D is used to simulate up to 106 atoms, where strain is computed in the valence-force field and electronic structure in the sp3d5s* model.

Measurement of the thermal conductance of silicon nanowires at low temperature

Abstract: We have performed thermal conductance measurements on individual single-crystalline silicon suspended nanowires. The nanowires (130nm thick and 200nm wide) are fabricated by e-beam lithography and suspended between two separated pads on silicon on insulator substrate. We measure the thermal conductance of the phonon waveguide by the 3ω method. The cross section of the nanowire approaches the dominant phonon wavelength in silicon which is of the order of 100nm at 1K. Above 1.3K the conductance behaves as T3, but a deviation is measured at the lowest temperature which can be attributed to the reduced geometry.

Method for producing single crystal silicon solar cell and single crystal silicon solar cell

Abstract: There is disclosed a method for producing a single crystal silicon solar cell comprising the steps of: implanting hydrogen ions or rare gas ions into a single crystal silicon substrate through an ion implanting surface thereof to form an ion implanted layer in the single crystal silicon substrate; closely contacting the single crystal silicon substrate and a transparent insulator substrate with each other via a transparent adhesive while using the ion implanting surface as a bonding surface; curing the transparent adhesive; applying an impact to the ion implanted layer to mechanically delaminate the single crystal silicon substrate thereat to leave a single crystal silicon layer; forming a plurality of diffusion regions having a second conductivity type at the delaminated surface side of the single crystal silicon layer, in a manner that a plurality of first conductivity-type regions and a plurality of second conductivity-type regions are present at the delaminated surface of the single crystal silicon layer; forming pluralities of individual electrodes on the pluralities of first and second conductivity-type regions of the single crystal silicon layer, respectively; and forming collector electrodes for the individual electrodes, respectively. There can be provided a single crystal silicon solar cell as a see-through type solar cell, including a thin-film light conversion layer made of single crystal silicon having a higher crystallinity.

Strained-silicon cmos device and method

Abstract: The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

Solid phase epitaxy versus random nucleation and growth in sub-20nm wide fin field-effect transistors

Abstract: The authors investigate the implications of amorphizing ion implants on the crystalline integrity of sub-20nm wide fin field-effect transistors (FinFETs). Recrystallization of thin body silicon is not as straightforward as that of bulk silicon because the regrowth direction may be parallel to the silicon surface rather than terminating at it. In sub-20nm wide FinFETs surface proximity suppresses crystal regrowth and promotes the formation of twin boundary defects in the implanted regions. In the case of a 50nm amorphization depth, random nucleation and growth leads to polycrystalline silicon formation in the top ∼25nm of the fin, despite being only ∼25nm from the crystalline silicon seed.

Brother Silicon, Sister Germanium

Abstract: Material and lattice defect properties of silicon and germanium relevant for device processing are discussed and compared with respect to their impact on crystal pulling, device processing, and diode leakage current. It is shown that both semiconductors are very similar when comparing their material properties at the same temperature T normalized to the melt temperature T m . In other respects, however, like the diffusion of dopants, Ge behaves quite differently. With respect to diode leakage, germanium is more sensitive to metal contamination than silicon at the same device operation temperature.

Visualization of localized strain of a crystalline thin layer at the nanoscale by tip-enhanced Raman spectroscopy and microscopy

Abstract: Since the carrier mobility in a strained silicon thin layer is enhanced compared to unstrained layers, strained silicon is finding tremendous attention as a promising material for ultralarge integrated electronic circuits assembled on one substrate. These strained substrates, however, suffer from nanoscale fluctuation of strain distribution, which can strongly affect the performance of devices. Raman spectroscopy is a powerful tool because the optical phonons in the Raman spectra are strongly influenced by strain. However, Raman efficiency of a thin layer is extremely small and is often eclipsed under the Raman scattering of the underlying buffer substrates. Also, the spatial resolution is restricted by the diffraction limits of the probing light. Here, in this article we demonstrate the use of surface enhancement in Raman scattering to overcome both these problems. In the first step, a strained silicon thin layer was covered with a silver layer to invoke surface-enhanced Raman spectroscopy (SERS), and it was found that SERS can effectively enhance the Raman signal originating from the strained silicon layer, so that it stands distinctly apart from the background signal originating from the buffer layer. In the next step, we demonstrate the utilization of the same mechanism for a point surface enhancement, rather than a large surface enhancement. This is done by utilizing a silver-coated sharp tip, just like SERS, but only from the sample region very close to the tip apex. This technique, known as tip-enhanced Raman spectroscopy (TERS), provides nanometric resolution in our measurement. We observed localized strains by utilizing TERS. The TERS spectra revealed clear nanoscale variation in the Raman wavenumber. Micro-Raman measurements, however, show only uniform features because of the averaging effect due to the diffraction limit of light. For further improvement of TERS on silicon materials, we discuss the utilization of shorter wavelength, specialized tip, tip-pressure effect, and depolarization configurations. Copyright © 2007 John Wiley & Sons, Ltd.

Tri-gate patterning using dual layer gate stack

Abstract: In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

A comparison of zinc oxide thin-film transistors on silicon oxide and silicon nitride gate dielectrics

Abstract: We compared the properties of ZnO thin-film transistors in the inverted coplanar geometry on thermally grown silicon oxide gate dielectric to devices on silicon nitride, grown by plasma-enhanced chemical vapor deposition at 150 °C or magnetron sputtering at room temperature. The ZnO semiconductor was sputtered without substrate heating at oxygen partial pressures in the range of 10−5−10−4 Torr. At the lowest oxygen partial pressure, transistor characteristics were similar for all dielectrics. The field-effect mobility approached ∼5 cm2/V s and devices generally operated in depletion mode. With increasing oxygen partial pressure, the mobility decreased by 1000× on SiO2, whereas the decrease on silicon nitride was considerably smaller. On SiO2 the threshold voltage was >30 V but <5 V on silicon nitride. Devices on SiO2 operated in enhancement mode, whereas they operated in depletion mode on PECVD silicon nitride. Photoluminescence of ZnO revealed that deep-level emission depended on the specific dielectric ...

Stability of nanocrystalline silicon bottom-gate thin film transistors with silicon nitride gate dielectric

Abstract: We report on the stability of nanocrystalline silicon (nc-Si) bottom-gate (BG) thin film transistors (TFTs) with various compositions of hydrogenated amorphous silicon nitride (a-SiNx:H) gate dielectric TFTs with nitrogen-rich nitride exhibit higher output transconductance, threshold voltage stability, and effective field effect mobility (μFE) than the devices with silicon-rich gate dielectric For example, μFE drops from 075to02cm2∕Vs when the gate dielectric composition [N]∕[Si] changes from 13 to 1 The corresponding threshold voltages (VT) are 4 and −2V Following 5h electrical stress tests, the shift in threshold voltage (ΔVT) is larger for dielectrics with lower [N]∕[Si] content, regardless of the operating regime Indeed, ΔVT in the saturation regime is considerably less and correlates with the charge concentration in the channel, ie, ΔVT in saturation is about 2∕3 of that in the linear regime Relaxation tests on the stressed TFTs show that the charge trapping is the instability mechanism in

Low defect si:c layer with retrograde carbon profile

Abstract: Formation of carbon-substituted single crystal silicon layer is prone to generation of large number of defects especially at high carbon concentration. The present invention provides structures and methods for providing low defect carbon-substituted single crystal silicon layer even for high concentration of carbon in the silicon. According to the present invention, the active retrograde profile in the carbon implantation reduces the defect density in the carbon-substituted single crystal silicon layer obtained after a solid phase epitaxy. This enables the formation of semiconductor structures with compressive stress and low defect density. When applied to semiconductor transistors, the present invention enables N-type field effect transistors with enhanced electron mobility through the tensile stress that is present into the channel.

Multilayer 3-D photonics in silicon.

Abstract: Three-dimensionally (3-D) integrated photonic structures in multiple layers of silicon are reported. Implantation of oxygen ions into a silicon-on-insulator substrate with a patterned thermal oxide mask, followed by a high temperature anneal, creates photonic structures on 3-D integrated layers of silicon. This process is combined with epitaxial growth to achieve devices on three vertically integrated layers of silicon. As a demonstration vehicle, we report a multistage optical filter that comprises of coupled microdisks on two subsurface silicon layers with bus waveguides on the surface (3rd) layer. The optical filter shows extinction ratios in excess of 14 dB, with excess insertion loss of less than 1 dB.

Silicon single crystal wafer for igbt and method for manufacturing silicon single crystal wafer for igbt

Abstract: In this silicon single crystal wafer for IGBT, COP defects and dislocation clusters are eliminated from the entire region in the radial direction of the crystal, the interstitial oxygen concentration is 8.5×1017 atoms/cm3 or less, and variation in resistivity within the wafer surface is 5% or less. This method for manufacturing a silicon single crystal wafer for IGBT includes introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5×1017 atoms/cm3 or less at a silicon single crystal pulling speed enabling pulling of a silicon single crystal free of grown-in defects. The pulled silicon single crystal is irradiated with neutrons so as to dope with phosphorous; or an n-type dopant is added to the silicon melt; or phosphorous is added to the silicon melt so that the phosphorous concentration in the silicon single crystal is 2.9×1013 to 2.9×1015 atoms/cm3 and a p-type dopant having a segregation coefficient smaller than that of the phosphorous is added to the silicon melt so that the concentration in the silicon single crystals is 1×1013 to 1×1015 atoms/cm3 corresponding to the segregation coefficient thereof.

Tunnel effect transistors based on silicon nanowires

Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

Abstract: The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.

Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

Abstract: This paper presents a study on the effectiveness of strained contact-etch-stop-layer (CESL) technologies in aggressively scaled dense structures. The focus is on nested transistors, which is a technologically very important structure that consists of a chain of gates on one active area. It will be shown that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations, which accordingly leads to different scaling guidelines to obtain a layout-insensitive strained CESL technology. Decreasing the CESL thickness is not enough for technology scaling; also, adapting the spacer dimensions is indispensable to scale a strained CESL technology from one technology node to the next.

Electron Transport in Strained-Silicon Directly on Insulator Ultrathin-Body n-MOSFETs With Body Thickness Ranging From 2 to 25 nm

Abstract: The electron effective mobility in ultrathin-body n-channel metal-oxide-semiconductor field-effect transistors fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage measurements as well as cross-sectional transmission electron microscopy. Devices with body thicknesses ranging from 2 to 25 nm are studied. Significant mobility enhancements ( ~1.8x) compared to unstrained SOI are observed for 30% SSDOI with body thicknesses of above 3.5 nm. The mobility exhibits a sharp drop as the body thickness is scaled below 3.5 nm

Germanium-rich silicon-germanium films epitaxially grown by ultrahigh vacuum chemical-vapor deposition directly on silicon substrates

Abstract: We have grown device quality germanium-rich silicon-germanium films on silicon substrates using a two-step ultrahigh vacuum chemical-vapor deposition growth process. The films have thermally induced tensile strain, resulting in a direct band gap reduction of ∼30meV, in agreement with what we observe for similarly grown pure germanium films. Our data suggest that alloying of silicon increases the band gap reduction with strain at the high germanium end of the composition range. Annealing of the films allows for reduction in the dislocation density to 2×107∕cm2, comparable to what we achieve in pure germanium films and showing that alloying small amounts of silicon does not inhibit dislocation motion. p-i-n diodes fabricated from these films using a silicon compatible process exhibit reverse leakage currents of ∼10mA∕cm2 at 0.5V reverse bias. The responsivity of a Si0.04.8Ge0.952 diode was measured at 0.23A∕W at 1280nm, demonstrating the high quality of these epitaxial films.

A method for fabricating a gate dielectric layer utilized in a gate structure

Abstract: Methods for forming a gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a silicon substrate, depositing a silicon nitride layer on the silicon oxide layer by a thermal process, wherein the silicon oxide layer and the silicon nitride layer are utilized as a gate dielectric layer in a gate structure, and thermally annealing the substrate. In another embodiment, the method includes forming a silicon oxide layer on the silicon substrate with a thickness less than 15 A, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer with a thickness less than 15 A by a thermal process, wherein the silicon oxide layer and the silicon nitride layer are utilized as a gate dielectric layer in a gate structure, plasma treating the silicon nitride layer; and thermally annealing the substrate.

Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy

Abstract: Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE) technique for the first time. The very simple process uses no recess etch or epi deposition steps, adds minimal process cost, and can be easily integrated into a standard CMOS process. With a record high 1.65 at% substitutional C concentration in source and drain, 615 MPa uniaxial tensile stress was introduced in the channel, leading to a 35% improvement in electron mobility and 6% and 15% current drive increase in sub-40 and 200 nm channel length devices respectively.

Forming a non-planar transistor having a quantum well channel

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Mos device structure

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Method of manufacturing crystalline silicon solar cells with improved surface passivation

Abstract: The present invention provides a method of manufacturing a crystalline silicon solar cell, comprising: - providing a crystalline silicon substrate having a front side and a back side; - forming a thin silicon oxide film on at least one of the front and the back side by soaking the crystalline silicon substrate in a chemical solution; - forming a dielectric coating film on the thin silicon oxide film on at least one of the front and the back side. The thin silicon oxide film may be formed with a thickness of 0.5-10 nm. By forming a oxide layer using a chemical solution, it is possible to form a thin oxide film for surface passivation wherein the relatively low temperature avoids deterioration of the semiconductor layers.

Silicon layer for stopping dislocation propagation

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.