Showing papers on "Wafer published in 2013"

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Abstract: Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

Band-Like Transport in High Mobility Unencapsulated Single-Layer MoS2 Transistors

Abstract: Ultra-thin MoS2 has recently emerged as a promising two-dimensional semiconductor for electronic and optoelectronic applications. Here, we report high mobility (>60 cm2/Vs at room temperature) field-effect transistors that employ unencapsulated single-layer MoS2 on oxidized Si wafers with a low level of extrinsic contamination. While charge transport in the sub-threshold regime is consistent with a variable range hopping model, monotonically decreasing field-effect mobility with increasing temperature suggests band-like transport in the linear regime. At temperatures below 100 K, temperature-independent mobility is limited by Coulomb scattering, whereas, at temperatures above 100 K, phonon-limited mobility decreases as a power law with increasing temperature.

Layer-Controlled, Wafer-Scale, and Conformal Synthesis of Tungsten Disulfide Nanosheets Using Atomic Layer Deposition

Abstract: The synthesis of atomically thin transition-metal disulfides (MS2) with layer controllability and large-area uniformity is an essential requirement for their application in electronic and optical devices. In this work, we describe a process for the synthesis of WS2 nanosheets through the sulfurization of an atomic layer deposition (ALD) WO3 film with systematic layer controllability and wafer-level uniformity. The X-ray photoemission spectroscopy, Raman, and photoluminescence measurements exhibit that the ALD-based WS2 nanosheets have good stoichiometry, clear Raman shift, and bandgap dependence as a function of the number of layers. The electron mobility of the monolayer WS2 measured using a field-effect transistor (FET) with a high-k dielectric gate insulator is shown to be better than that of CVD-grown WS2, and the subthreshold swing is comparable to that of an exfoliated MoS2 FET device. Moreover, by utilizing the high conformality of the ALD process, we have developed a process for the fabrication of...

Atomic layer lithography of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves

Abstract: Squeezing light through nanometre-wide gaps in metals can lead to extreme field enhancements, nonlocal electromagnetic effects and light-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists because of the lack of reliable technology to fabricate uniform nanogaps with atomic-scale resolution and high throughput. Here we introduce a new patterning technology based on atomic layer deposition and simple adhesive-tape-based planarization. Using this method, we create vertically oriented gaps in opaque metal films along the entire contour of a millimetre-sized pattern, with gap widths as narrow as 9.9 A, and pack 150,000 such devices on a 4-inch wafer. Electromagnetic waves pass exclusively through the nanogaps, enabling background-free transmission measurements. We observe resonant transmission of near-infrared waves through 1.1-nm-wide gaps (λ/1,295) and measure an effective refractive index of 17.8. We also observe resonant transmission of millimetre waves through 1.1-nm-wide gaps (λ/4,000,000) and infer an unprecedented field enhancement factor of 25,000.

Compact and low loss Y-junction for submicron silicon waveguide

Abstract: A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

A Graphene-Based Hot Electron Transistor

Abstract: We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).

Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics

Abstract: Epitaxial lift-off process enables the separation of III-V device layers from gallium arsenide substrates and has been extensively explored to avoid the high cost of III-V devices by reusing the substrates. Conventional epitaxial lift-off processes require several post-processing steps to restore the substrate to an epi-ready condition. Here we present an epitaxial lift-off scheme that minimizes the amount of post-etching residues and keeps the surface smooth, leading to direct reuse of the gallium arsenide substrate. The successful direct substrate reuse is confirmed by the performance comparison of solar cells grown on the original and the reused substrates. Following the features of our epitaxial lift-off process, a high-throughput technique called surface tension-assisted epitaxial lift-off was developed. In addition to showing full wafer gallium arsenide thin film transfer onto both rigid and flexible substrates, we also demonstrate devices, including light-emitting diode and metal-oxide-semiconductor capacitor, first built on thin active layers and then transferred to secondary substrates.

Direct Growth of Graphene Film on Germanium Substrate

Abstract: Graphene has been predicted to play a role in post-silicon electronics due to the extraordinary carrier mobility. Chemical vapor deposition of graphene on transition metals has been considered as a major step towards commercial realization of graphene. However, fabrication based on transition metals involves an inevitable transfer step which can be as complicated as the deposition of graphene itself. By ambient-pressure chemical vapor deposition, we demonstrate large-scale and uniform depositon of high-quality graphene directly on a Ge substrate which is wafer scale and has been considered to replace conventional Si for the next generation of high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The immiscible Ge-C system under equilibrium conditions dictates graphene depositon on Ge via a self-limiting and surface-mediated process rather than a precipitation process as observed from other metals with high carbon solubility. Our technique is compatible with modern microelectronics technology thus allowing integration with high-volume production of complementary metal-oxide-semiconductors (CMOS).

Materials and Fabrication Processes for Transient and Bioresorbable High-Performance Electronics

Abstract: Materials and fabrication procedures are described for bioresorbable transistors and simple integrated circuits, in which the key processing steps occur on silicon wafer substrates, in schemes compatible with methods used in conventional microelectronics. The approach relies on an unusual type of silicon on insulator wafer to yield devices that exploit ultrathin sheets of monocrystalline silicon for the semiconductor, thin films of magnesium for the electrodes and interconnects, silicon dioxide and magnesium oxide for the dielectrics, and silk for the substrates. A range of component examples with detailed measurements of their electrical characteristics and dissolution properties illustrate the capabilities. In vivo toxicity tests demonstrate biocompatibility in sub-dermal implants. The results have significance for broad classes of water-soluble, “transient” electronic devices.

Using nanoscale thermocapillary flows to create arrays of purely semiconducting single-walled carbon nanotubes

Abstract: Thermocapillary effects allow for the selective removal of metallic nanotubes from semiconducting ones, which occurs directly on a wafer substrate.

Ultra-thin DVS-BCB adhesive bonding of III-V wafers, dies and multiple dies to a patterned silicon-on-insulator substrate

Abstract: Heterogeneous integration of III-V semiconductor materials on a silicon-on-insulator (SOI) platform has recently emerged as one of the most promising methods for the fabrication of active photonic devices in silicon photonics. For this integration, it is essential to have a reliable and robust bonding procedure, which also provides a uniform and ultra-thin bonding layer for an effective optical coupling between III-V active layers and SOI waveguides. A new process for bonding of III-V dies to processed silicon-on-insulator waveguide circuits using divinylsiloxane-bis-benzocyclobutene (DVS-BCB) was developed using a commercial wafer bonder. This “cold bonding” method significantly simplifies the bonding preparation for machine-based bonding both for die and wafer-scale bonding. High-quality bonding, with ultra-thin bonding layers (<50 nm) is demonstrated, which is suitable for the fabrication of heterogeneously integrated photonic devices, specifically hybrid III-V/Si lasers.

Large-area free-standing ultrathin single-crystal silicon as processable materials.

Abstract: Silicon has been driving the great success of semiconductor industry, and emerging forms of silicon have generated new opportunities in electronics, biotechnology, and energy applications. Here we demonstrate large-area free-standing ultrathin single-crystalline Si at the wafer scale as new Si materials with processability. We fabricated them by KOH etching of the Si wafer and show their uniform thickness from 10 to sub-2 μm. These ultrathin Si exhibits excellent mechanical flexibility and bendability more than those with 20–30 μm thickness in previous study. Unexpectedly, these ultrathin Si materials can be cut with scissors like a piece of paper, and they are robust during various regular fabrication processings including tweezer handling, spin coating, patterning, doping, wet and dry etching, annealing, and metal deposition. We demonstrate the fabrication of planar and double-sided nanocone solar cells and highlight that the processability on both sides of surface together with the interesting property...

Graphene oxide film as solid lubricant.

Abstract: As a layered material, graphene oxide (GO) film is a good candidate for improving friction and antiwear performance of silicon-based MEMS devices. Via a green electrophoretic deposition (EPD) approach, GO films with tunable thickness in nanoscale are fabricated onto silicon wafer in a water solution. The morphology, microstructure, and mechanical properties as well as the friction coefficient and wear resistance of the films were investigated. The results indicated that the friction coefficient of silicon wafer was reduced to 1/6 its value, and the wear volume was reduced to 1/24 when using GO film as solid lubricant. These distinguished tribology performances suggest that GO films are expected to be good solid lubricants for silicon-based MEMS/NEMS devices.

Microstructures for improved wafer handling

Abstract: Provided herein are high coefficient of friction contact surfaces for transfer of substrates including semiconductor wafers. In certain implementations, the contact surfaces include microstructures that exploit intermolecular surface forces for increased adhesion and friction in the x-y direction during substrate transfer, while allowing easy release in the z-direction without tilting the substrate. Also provided are robot end effectors including the contact surfaces and related high-throughput transfer systems and methods.

Bioinspired Wafer‐Scale Production of Highly Stretchable Carbon Films for Transparent Conductive Electrodes

Abstract: Flexible transparent and conductive films (TCFs) are essential elements of the next-generation flexible devices, including touch screens and displays, organic light-emitting diodes (OLEDs), solar cells (SCs), organic field-effect transistors (OFETs), and sensors. Indium tin oxide (ITO) has been the most widely used TCF in optoelectronic devices for almost four decades, owing to its low sheet resistance (Rs 10 W/&) coupled with high transmittance (T 80%). However, ITO suffers from inherent brittleness, which makes it unsuitable for flexible devices. In the race to replace ITO, networks of metal nanowires and carbon nanotubes are leading the pack; however, their high costs of synthesis and high surface roughness hamper their commercial applications. 4] Graphene and graphene-based thin films have been recognized as attractive alternatives because of their outstanding electronic, optoelectronic, and mechanical properties. Although sheet resistance as low as 30 W/& (at T= 90 %) has been obtained for graphene grown on metallic substrates, the multitransfer process associated with the additional chemical doping increases the costs dramatically. The establishment of facile, yet controllable methods for the large-area production of flexible TCFs at low costs remains a challenging task. The molecular precursor approach, namely the production of carbon-based TCFs using aromatic-rich precursors as the carbon source seems to be much less explored. Through the thermal treatment of properly selected organic precursors, this synthetic method offers an intriguing means to lowcosts processing and structural control of highly conductive carbon/graphene films, which are difficult to achieve using methods such as chemical vapor deposition (CVD), epitaxial growth, liquid exfoliation, and reduction of graphene oxide (GO) film. Nevertheless, the bottleneck associated with this method lies in the relatively low electrical conductivity of the produced TCFs (e.g., 206 Scm 1 for a pyrolyzed film of a giant polycyclic aromatic hydrocarbon). Recently, inspired by the adhesive proteins secreted by marine mussels, polydopamine (PDA) has proven to be a material for facile and universal surface coating. By selfpolymerization of dopamine, PDA that sticks to the surface of virtually all types of solid materials regardless of their chemical nature, can be produced. 14] The self-polymerization reaction is so mild that simple immersion of substrates in an aqueous solution of dopamine results in the spontaneous deposition of PDA film. 14] The film is layer-structured and the thickness can be tailored at the nanometer scale. PDA is mainly composed of cross-linked indolequinone units (Figure 1, the definitive atomic scale structure of

Flat sic semiconductor substrate

Abstract: Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR). The resulting SiC wafer has a mirror-like surface that is fit for epitaxial deposition of SiC. The specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR) of the wafer are preserved following the addition of the epitaxy layer.

Methods and apparatus for plasma-based deposition

Abstract: High-deposition rate methods for forming transparent ashable hardmasks (AHMs) that have high plasma etch selectivity to underlying layers are provided. The methods involve placing a wafer on a powered electrode such as a powered pedestal for plasma-enhanced deposition. According to various embodiments, the deposition is run at low hydrocarbon precursor partial pressures and/or low process temperatures. Also provided are ceramic wafer pedestals with multiple electrode planes embedded with the pedestal are provided. According to various embodiments, the pedestals have multiple RF mesh electrode planes that are connected together such that all the electrode planes are at the same potential.

Au-Free AlGaN/GaN Power Diode on 8-in Si Substrate With Gated Edge Termination

Abstract: High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

Ultrathin, high-efficiency, broad-band, omni-acceptance, organic solar cells enhanced by plasmonic cavity with subwavelength hole array.

Abstract: Three of central challenges in solar cells are high light coupling into solar cell, high light trapping and absorption in a sub-absorption-length-thick active layer, and replacement of the indium-tin-oxide (ITO) transparent electrode used in thin-film devices. Here, we report a proposal and the first experimental study and demonstration of a new ultra-thin high-efficiency organic solar cell (SC), termed "plasmonic cavity with subwavelength hole-array (PlaCSH) solar cell", that offers a solution to all three issues with unprecedented performances. The ultrathin PlaCSH-SC is a thin plasmonic cavity that consists of a 30 nm thick front metal-mesh electrode with subwavelength hole-array (MESH) which replaces ITO, a thin (100 nm thick) back metal electrode, and in-between a polymer photovoltaic active layer (P3HT/PCBM) of 85 nm thick (1/3 average absorption-length). Experimentally, the PlaCSH-SCs have achieved (1) light coupling-efficiency/absorptance as high as 96% (average 90%), broad-band, and Omni acceptance (light coupling nearly independent of both light incident angle and polarization); (2) an external quantum efficiency of 69% for only 27% single-pass active layer absorptance; leading to (3) a 4.4% power conversion efficiency (PCE) at standard-solar-irradiation, which is 52% higher than the reference ITO-SC (identical structure and fabrication to PlaCSH-SC except MESH replaced by ITO), and also is among the highest PCE for the material system that was achievable previously only by using thick active materials and/or optimized polymer compositions and treatments. In harvesting scattered light, the Omni acceptance can increase PCE by additional 81% over ITO-SC, leading to a total 175% increase (i.e. 8% PCE). Furthermore, we found that (a) after formation of PlaCSH the light reflection and absorption by MESH are reduced by 2 to 6 fold from the values when it is alone; and (b) the sheet resistance of a 30 nm thick MESH is 2.2 ohm/sq or less-4.5 fold or more lower than the best reported value for a 100 nm thick ITO film, giving a lowest reflectance-sheet-resistance product. Finally, fabrication of PlaCSH has used nanoimprint on 4" wafer and is scalable to roll-to-roll manufacturing. The designs, fabrications, and findings are applicable to thin solar cells in other materials.

Fabrication of GaInP/GaAs//Si Solar Cells by Surface Activated Direct Wafer Bonding

Abstract: GaInP/GaAs//Si solar cells with three active p-n junctions were fabricated by surface activated direct wafer bonding between GaAs and Si. The direct wafer bond is performed at room temperature and leads to a conductive and transparent interface. This allows the fabrication of high-efficiency monolithic tandem solar cells with active junctions in both Si and the III-V materials. This technology overcomes earlier challenges of III-V and Si integration caused by the large difference in lattice constant and thermal expansion. Transmission electron microscopy revealed a 5-nm thin amorphous interface layer formed by the argon fast atom beam treatment before bonding. No further defects or voids are detected in the photoactive layers. First triple-junction solar cell devices on Si reached an efficiency of 23.6% under concentrated illumination.

A Fill Factor Loss Analysis Method for Silicon Wafer Solar Cells

Abstract: The fill factor of silicon wafer solar cells is strongly influenced by recombination currents and ohmic resistances. A practical upper limit for the fill factor of crystalline silicon solar cells operating under low-level injection is set by recombination in the quasi-neutral bulk and at the two cell surfaces. Series resistance, shunt resistance, and additional recombination currents further lower the fill factor. For process optimization or loss analysis of solar cells, it is important to determine the influence of both ohmic and recombination loss mechanisms on the fill factor. In this paper, a method is described to quantify the loss in fill factor due to series resistance, shunt resistance, and additional recombination currents. Only the 1-Sun J-V curve, series resistance at the maximum power point, and shunt resistance need to be determined to apply the method. Application of the method is demonstrated on an 18.4% efficient inline-diffused p-type silicon wafer solar cell and a 21.1% efficient heterojunction n-type silicon wafer solar cell. Our analysis does not require J-V curve fitting to extract diode saturation current densities or ideality factor; however, the results are shown to be consistent with curve fitting results if the cell's two-diode model parameters can be unambiguously determined by curve fitting.

Mechanisms for room temperature direct wafer bonding

Abstract: Reducing the temperature needed for high strength bonding which was and is driven by the need to reduce effects of coefficient of thermal expansion mismatch, reduce thermal budgets, and increase throughput has led to the development of plasma treatment procedures capable of bonding Si wafers below 300 °C with a bond strength equivalent to Si bulk. Despite being widely used, the physical and chemical mechanisms enabling low temperature wafer bonding have remained poorly understood. We developed an understanding of the beneficial surface modifications by plasma and a model based on short range low temperature diffusion through bonding experiments combined with results from spectroscopic ellipsometry, depth resolving Auger electron spectroscopy, and transmission electron microscopy measurements. We also present experimental results showing that even at room temperature reasonable bond strength can be achieved. We conclude that the gap closing mechanism is therefore a process which balances the lowering of the total energy by minimizing the sum of the free surface energy (maximizing the contact area between the surfaces) and strain energy in the oxide at the bond interface.

Removal of native oxide with high selectivity

Abstract: Provided are methods and systems for removing a native silicon oxide layer on a wafer. In a non-sequential approach, a wafer is provided with a native silicon oxide layer on a polysilicon layer. An etchant including a hydrogen-based species and a fluorine-based species is introduced, exposed to a plasma, and flowed onto the wafer at a relatively low temperature. The wafer is then heated to a slightly elevated temperature to substantially remove the native oxide layer. In a sequential approach, a wafer is provided with a native silicon oxide layer. A first etchant including a hydrogen-based species and a fluorine-based species is flowed onto the wafer. Then the wafer is heated to a slightly elevated temperature, a second etchant is flowed towards the wafer, and the second etchant is exposed to a plasma to complete the removal of the native silicon oxide layer and to initiate removal of another layer such as a polysilicon layer.

Wafer processing chamber and method for transferring wafer in the same

Abstract: A wafer processing chamber and a method for transferring wafer in the same are provided to prevent the arcing issue. In the embodiments, a wafer is positioned on the focus ring, and a lifting apparatus is provided outside the wafer such as corresponding to the focus ring. The lifting apparatus of the embodiment could be positioned below or above the focus ring. The wafer and the focus ring are lifted together by the lifting apparatus, and transferred together by a transferring unit.

Control of Superhydrophilic and Superhydrophobic Graphene Interface

Abstract: Superhydrophobic and superhydrophilic properties of chemically-modified graphene have been achieved in larger-area vertically aligned few-layer graphene nanosheets (FLGs), prepared on Si (111) substrate by microwave plasma chemical vapor deposition (MPCVD). Furthermore, in order to enhance wettability, silicon wafers with microstructures were fabricated, on which graphene nanosheets were grown and modified by a chemical method to form hydrophilic and hydrophobic structures. A superhydrophilic graphene surface (contact angle 0°) and a superhydrophobic graphene surface (contact angle 152.0°) were obtained. The results indicate that the microstructured silicon enhances the hydrophilic and hydrophobic wettabilities significantly.

Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

Abstract: A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.

Deposition chambers with UV treatment and methods of use

Abstract: Described are apparatus and methods for processing semiconductor wafers so that a film can be deposited on the wafer and the film can be UV treated without the need to move the wafer to a separate location for treatment. The apparatus and methods include a window which is isolated from the reactive gases by a flow of an inert gas.

Integrated antennas in wafer level package

Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.

Surface Passivation of Efficient Nanotextured Black Silicon Solar Cells Using Thermal Atomic Layer Deposition

Abstract: Efficient nanotextured black silicon solar cells passivated by an Al2O3 layer are demonstrated. The broadband antireflection of the nanotextured black silicon solar cells was provided by fabricating vertically aligned silicon nanowire (SiNW) arrays on the n+ emitter. A highly conformal Al2O3 layer was deposited upon the SiNW arrays by the thermal atomic layer deposition (ALD) based on the multiple pulses scheme. The nanotextured black silicon wafer covered with the Al2O3 layer exhibited a low total reflectance of ∼1.5% in a broad spectrum from 400 to 800 nm. The Al2O3 passivation layer also contributes to the suppressed surface recombination, which was explored in terms of the chemical and field-effect passivation effects. An 8% increment of short-circuit current density and 10.3% enhancement of efficiency were achieved due to the ALD Al2O3 surface passivation and forming gas annealing. A high efficiency up to 18.2% was realized in the ALD Al2O3-passivated nanotextured black silicon solar cells.