Teradyne

About: Teradyne is a company organization based out in Boston, Massachusetts, United States. It is known for research contribution in the topics: Signal & Automatic test equipment. The organization has 828 authors who have published 999 publications receiving 15695 citations.

Flexible approach for representing different bus protocols

Abstract: A method for flexibly defining communication constructs includes providing at least one communication element type for at least one layer of a generalized communication model, such as a bus model. Each communication element type has a user-definable structure that is adaptable for representing a corresponding protocol layer of a target communication medium. Users can define specific communication element types to substantially represent the target protocol. Users can also define the communication element types to depart from the target protocol in precisely defined ways.

Single axis manipulator with controlled compliance

Abstract: A semiconductor test system that includes a tester (150), a material handling unit (100) and a manipulator that positions the tester relative to the material handling unit (100). The manipulator is in the form of a cart that can be wheeled to the material handling unit. The cart is attached to the material handling unit (100) to provide course positioning of the tester relative to the handling unit. Major motion of the test head is constrained to an axis perpendicular to the mating interface of the material handling unit. However, compliant motion, with up to six degrees of freedom, is possible in a complaint zone near the handler. In this way, alignment units on the tester and material handling unit can accurately control the final positioning of the tester relative to the material handling unit.

Thermal control of a probe card assembly

Abstract: An example test system includes a test head and a probe card assembly connected to the test head. The probe card assembly includes: a probe card having electrical contacts, a stiffener connected to the probe card to impart rigidity to the probe card, and a heater to heat to at least part of the probe card assembly. A prober is configured to move a device under test (DUT) into contact with the electrical contacts of the probe card assembly.

Ternary search process

Abstract: An apparatus for use in obtaining a value from a device includes a first comparator to receive a reference high signal and a device signal, where the first comparator provides a first output signal to indicate whether the device signal is above or below the reference high signal, and a second comparator to receive a reference low signal and the device signal, where the second comparator provides a second output signal to indicate whether the device signal is above or below the reference low signal. Also included in the apparatus is circuitry (i) to adjust at least one of the reference high signal and the reference low signal based on the first output signal and the second output signal, and (ii) to output the value if a difference between the reference high signal and the reference low signal meets a predetermined criterion, the value being based on the difference.

Method and apparatus for device testing using multiple processing paths

Abstract: According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.