Teradyne

About: Teradyne is a company organization based out in Boston, Massachusetts, United States. It is known for research contribution in the topics: Signal & Automatic test equipment. The organization has 828 authors who have published 999 publications receiving 15695 citations.

Bussing construction for printed circuit connectors

Abstract: A bussing construction for printed circuit card connectors arrayed on the front face of a panel forming a connector plane provides bus bars above the plane and extending adjacent the connector ends, with clips on the connectors mounting the bus bars to the connectors. The connectors also mount distribution conductors above the connector plane and connecting the bus bars to distribution contacts seated in the connector sockets.

Methods of manufacturing an electrical connector incorporating passive circuit elements

Abstract: A process for manufacturing an electrical connector is described. In the preferred embodiment, the process includes the following steps: (a) providing a lead frame that has a plurality of signal conductors, where each of the signal conductors has a first contact end, a second contact end and an intermediate portion therebetween; (b) providing at least a segment of the intermediate portion of the signal conductors with solder wettable material; (c) providing an insulative housing around at least a portion of each of the plurality of signal conductors, the insulative housing providing openings through which an exposed area of each of the signal conductors is accessible, where the exposed area includes the segment of the intermediate portion with solder wettable material; (d) cutting and removing a portion of the exposed area of the signal conductors such that only a portion of the exposed area remains; and (e) attaching a passive circuit element to the remaining portion of the exposed area of each of the signal conductors.

Apparatus and method for providing a programmable delay with low fixed delay

Abstract: A printed circuit board tester that compensates for the different propagation length of each channel including a single-input delay cell, at least one multiple-input delay cell, and a multiplexor. The delay cells are connected to one another in a chain. Further, the single-input delay cell is the first delay cell in the chain, and each multiple-input delay cell has the ability to select one of its inputs. A timing signal is applied to each delay cell, and to the multiplexor. The inputs of the multiple-input delay cells are connected to the output of the single-input delay cell, and to the outputs of any preceding multiple-input delay cells in the chain. The single-input delay cell delays the timing signal. Each multiple-input delay cell is programmed by the tester to select one of its inputs; it then delays the selected input. Finally, the multiplexor is programmed by the tester to select either the timing signal or one of the outputs of the delay cells. The signal selected by the multiplexor is the timing signal delayed by an amount necessary to compensate for the propagation length of the channel.

Apparatus and method for performing digital signal processing in an electronic circuit tester

Abstract: An electronic circuit tester for performing digital signal processing on signals generated by an electronic circuit including a multi-processor test computer, a plurality of driver/receiver channels, a plurality of capture instruments, and a plurality of high speed data paths. Capture instruments are programmed by the tester to sample a signal generated by an electronic circuit under test, convert the samples to digital form if necessary, and store the data samples in memory. The data samples are then moved from the memory of the capture instruments to the main memory of the multi-processor for analysis using digital signal processing techniques. After the initial group of data samples are moved from the capture instruments to main memory, subsequent programming of capture instruments and sampling of signals are performed concurrently with the movement and analysis of data samples. Multiple processors and multiple high speed data paths are preferably used to optimize test program throughput.

Method of making memory chips using memory tester providing fast repair

Abstract: A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified. In cases where multiple structures have the same highest priority, alternative criteria are used to select a single element for replacement. Preprocessing is used to focus, at each iteration, on the best faulty elements to replace. One preprocessing technique is to constrain the choice for replacement to faulty cells within certain clusters, which, based on the distribution of failures will require either a row or column for repair. Another preprocessing technique is to constrain the choice for replacement to faulty cells within a segment which must use either a row or column for repair. When the choice for replacement in a group of faulty cells is constrained to faulty cells which require a redundant row or column for repair, only the priorities of the rows or columns, respectively, in that group of cells is considered.