scispace - formally typeset
Search or ask a question
Institution

Teradyne

CompanyBoston, Massachusetts, United States
About: Teradyne is a company organization based out in Boston, Massachusetts, United States. It is known for research contribution in the topics: Signal & Automatic test equipment. The organization has 828 authors who have published 999 publications receiving 15695 citations.


Papers
More filters
Patent
Augarten Michael Heath1
29 Jan 1993
TL;DR: Memory test apparatus including a redundancy analyzer with a catch RAM transfer interface circuit receiving fault information for a plurality of regions of a memory under test simultaneously in parallel and transmitting the information for each region to a respective one of the region modules that each has a region input circuit, a region fault RAM, and a microprocessor connected to have access to the region Fault RAM.
Abstract: Memory test apparatus including a redundancy analyzer with a catch RAM transfer interface circuit receiving fault information for a plurality of regions of a memory under test simultaneously in parallel and transmitting the information for each region to a respective one of a plurality of region modules that each has a region input circuit, a region fault RAM, and a microprocessor connected to have access to the region fault RAM, the region fault RAMs storing fault addresses identifying the locations of faults in the memory under test.

40 citations

Patent
Toshihide Kadota1
31 Mar 2005
TL;DR: In this article, a method and system for measuring a device under test includes connecting a first test instrument and a second test instrument to a programmable logic device, which is configured to comply with interface specifications of the first instrument.
Abstract: A method and system for measuring a device under test includes connecting a first test instrument and a second test instrument to a programmable logic device. The programmable logic device is configured to comply with interface specifications of the first test instrument. The second test instrument has interface specifications that are different from the interface specifications of the first test instrument. The programmable logic device is configured to comply with the interface specifications of the second test instrument.

39 citations

Patent
William Earle Howard1
29 Jun 2000
TL;DR: In this paper, a self retained pressure connector is provided that includes a spring action contact surface at first end and a compliant interference fit surface at a second end, which is supported within a conductive hole in a printed circuit board and the spring action surface contact provides an electrical connection to an electrical element disposed on a second surface.
Abstract: A self retained pressure connector is provided that includes a spring action contact surface at a first end and a compliant interference fit contact surface at a second end. The compliant interference fit contact is supported within a conductive hole in a printed circuit board and the spring action surface contact provides an electrical connection to a conductive element disposed on a second surface. The conductive element may, in alternate embodiments, be a surface pad on the second surface or a second self retained pressure connector rotated ninety degrees from the first self retained pressure connector. A differential self retained pressure connection is also described in which a dielectric material is used to electrically isolate a first half of the connector from a second half of the connector.

39 citations

Patent
George W. Conner1
01 May 1995
TL;DR: In this paper, a system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period was proposed, where each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals.
Abstract: A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals and local programmable delay means for providing a timing signal after a delay interval following each local output, the resolution of the local delay means being greater than that of the clock

39 citations

Patent
12 Oct 1999
TL;DR: In this paper, the authors describe a test procedure for testing a device using automatic test equipment (ATE), which includes memory having a test application stored therein, a test interface to connect to the device, and a processor coupled to the memory and test interface.
Abstract: The invention is directed to techniques for providing a test procedure for testing a device using automatic test equipment (ATE). An ATE system includes memory having a test application stored therein, a test interface to connect to the device, and a processor coupled to the memory and the test interface. The processor is configured to operate in accordance with the test application to (i) provide a series of instructions based on a test procedure defining a device testing task, and (ii) control the test interface based on the provided series of instructions in order to test the device. The test procedure includes multiple test elements. Each test element defines instructions and programmable input variables that direct the processor to perform a particular test operation of the device testing task. The user of the ATE system combines test elements when creating the test procedure rather than write code from scratch, or modify code of prewritten templates. Accordingly, the user does not need to possess knowledge of a programming language or low-level ATE component details.

39 citations


Authors

Showing all 830 results

NameH-indexPapersCitations
John H. Lienhard6841918058
Todd Austin5516720607
Alexander H. Slocum444499393
Scott C. Noble30983495
D. R. LaFosse261392555
Tongdan Jin261132326
Thomas S. Cohen24372490
Mark W. Gailus21541851
R. Ryan Vallance20871081
Richard F. Roth18371104
Sepehr Kiani1528672
Frank W. Ciarallo14441066
Brian S. Merrow1434621
Philip T. Stokoe13261238
Ernest P. Walker1222252
Network Information
Related Institutions (5)
Infineon Technologies
33.9K papers, 230K citations

73% related

Texas Instruments
39.2K papers, 751.8K citations

72% related

Intel
68.8K papers, 1.6M citations

71% related

TSMC
22.1K papers, 256K citations

71% related

Nortel
9.3K papers, 265.2K citations

71% related

Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20223
20218
202020
201914
201811
201715