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Institution

Teradyne

CompanyBoston, Massachusetts, United States
About: Teradyne is a company organization based out in Boston, Massachusetts, United States. It is known for research contribution in the topics: Signal & Automatic test equipment. The organization has 828 authors who have published 999 publications receiving 15695 citations.


Papers
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Patent
13 Apr 2011
TL;DR: In this article, an interposer is fabricated from a plurality of modules that may be assembled into a selected shape such that the assembled modules substantially fill the selected shape, e.g., a circle approximately the size of a semiconductor wafer.
Abstract: Apparatus and methods for fabricating an interposer that may be used in testing a large number of electronic circuits or devices in parallel. The interposer may be fabricated from a plurality of modules that may be assembled into a selected shape, such that the assembled modules substantially fill the selected shape, e.g., a circle approximately the size of a semiconductor wafer. The plurality of modules may be formed from a single base shape (e.g., formed from a single injection mold). A portion of the formed modules may be machined into a first machined shape, or first and second machined shapes. The assembled modules may include only the base shape and first machined shape or first and second machined shapes. The limited number of shapes can reduce fabrication costs for an interposer.

10 citations

Patent
Edward Garcia1, Brian S. Merrow1, Evgeny Polyakov1, Walter Vahey1, Eric L. Truebenbach1 
17 Apr 2009
TL;DR: In this article, a storage device testing system (100) includes at least one robotic arm (200) defining a first axis (205) substantially normal to a floor surface (10), the robotic arm is operable to rotate through a predetermined arc about and extend radially from the first axis.
Abstract: A storage device testing system (100) includes at least one robotic arm (200) defining a first axis (205) substantially normal to a floor surface (10). The robotic arm is operable to rotate through a predetermined arc about and extend radially from the first axis. Multiple racks (300) are arranged around the robotic arm for servicing by the robotic arm. Each rack houses multiple test slots (310) that are each configured to receive a storage device transporter (550) configured to carry a storage device (500) for testing.

10 citations

Patent
Fang Xu1
30 Dec 2006
TL;DR: In this paper, a technique for reducing errors in a parallel, time-interleaved analog-to-digital converter (PTIC) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC.
Abstract: A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to frequency and multiplied by correction matrices to yield a corrected, reconstructed power spectrum for the PTIC. The technique is especially effective at removing gain and phase errors introduced by individual ADCs of the PTIC, including gain and phase errors that vary with frequency.

10 citations

Proceedings ArticleDOI
01 Nov 1997
TL;DR: It is suggested that automated optical inspection (AOI) competes effectively to fill the in-circuit test gap and is considered high in strength, simplicity and universality.
Abstract: It is suggested that automated optical inspection (AOI) competes effectively to fill the in-circuit test gap. AOI adds no unwelcome technologies to the workplace. Its programming and its results are simple and understandable in visual terms. AOI is thus considered high in strength, simplicity and universality. It is expected to grow rapidly, driven by the never ending demand for strong, simple, universal inspection methods.

10 citations

Patent
25 Oct 2011
TL;DR: In this article, a test flow with multiple sub-flows is defined to define a flow domain, and a test block is executed concurrently using resources in the flow domain specific site regions.
Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows, the pins accessed in connection with each sub- flow may be identified to define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions also may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

10 citations


Authors

Showing all 830 results

NameH-indexPapersCitations
John H. Lienhard6841918058
Todd Austin5516720607
Alexander H. Slocum444499393
Scott C. Noble30983495
D. R. LaFosse261392555
Tongdan Jin261132326
Thomas S. Cohen24372490
Mark W. Gailus21541851
R. Ryan Vallance20871081
Richard F. Roth18371104
Sepehr Kiani1528672
Frank W. Ciarallo14441066
Brian S. Merrow1434621
Philip T. Stokoe13261238
Ernest P. Walker1222252
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20223
20218
202020
201914
201811
201715