Teradyne

About: Teradyne is a company organization based out in Boston, Massachusetts, United States. It is known for research contribution in the topics: Signal & Automatic test equipment. The organization has 828 authors who have published 999 publications receiving 15695 citations.

Storage Device Transport, Clamping And Testing

Abstract: A storage device transporter (400, 400b, 400c), for transporting a storage device (600) and for mounting a storage device within a test slot (500, 500b), includes a frame (410, 410b, 410c) configured to receive and support a storage device. The frame includes sidewalls (418, 425a, 425b, 429a, 429b) configured to receive a storage device there between and sized to be inserted into a test slot along with a storage device. The frame also includes a clamping mechanism (450) operatively associated with at least one of the sidewalls. The clamping mechanism includes a first engagement element (476, 700, 750) and a first actuator (454, 710, 760) operable to initiate movements of the first engagement element. The first actuator is operable to move the first engagement element into engagement with a test slot after a storage device being supported by the frame is arranged in a test position in a test slot.

Discrete fourier transform (DFT) leakage removal

Abstract: A technique for measuring spectral components, such as noise and distortion, of a non-coherently sampled test signal containing at least one tone of known frequency includes modeling the spectral components of the at least one tone, including the effects of leakage, based upon frequency of the at least one tone and a plurality of known sampling parameters. A DFT is taken of the sampled test signal, and the DFT is adjusted based on the modeled spectral components. The adjusted DFT is substantially leakage-free and directly reveals spectral components of the test signal, including low-power components that would ordinarily be lost in the leakage errors.

Differential receiver architecture

Abstract: A receiver circuit for a tester for electronic devices is provided. The receiver circuit includes a clock receiver that is adapted to receive a source synchronous clock signal from a device under test. The receiver circuit further includes a data receiver that is responsive to the clock circuit. The data receiver is adapted to receive at least one differential data signal from the device under test. The receiver circuit also includes a trigger receiver that is responsive to the clock circuit. The trigger receiver is adapted to receive a trigger signal from the device under test. Finally, the receiver circuit includes a control circuit that is coupled to the trigger receiver. The control circuit is adapted to generate a start alignment capture signal based on the received trigger signal to initiate capture of data received at the data receiver for comparison with expected values.

High speed tester with narrow output pulses

Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.

Current mirror compensation circuit and method

Abstract: A current compensation circuit for use with a current mirror is disclosed. The current mirror circuit has a current path defined by a first current mirror stage driving a second current mirror stage, the second current mirror stage is coupled to a supply voltage source. The current compensation circuit comprises an impedance divider coupled to the supply voltage and an output node. The impedance divider operates to generate a compensation signal at the node representative of voltage changes in the supply voltage source. The compensation circuit further includes a gain stage having an input coupled to the output node and a current output connected to the current path. The gain stage operates to generate a compensation current for application to the current path in response to the compensation signal.