Showing papers in "IEEE Transactions on Circuits and Systems in 2020"

Extended Dissipative Control for Singularly Perturbed PDT Switched Systems and its Application

Abstract: In this paper, a class of discrete-time singularly perturbed switched systems $\left ({\text {SPSSs}}\right) $ with persistent dwell-time $\left ({\text {PDT}}\right)$ switching law is firstly proposed. Using the slow-state feedback control method, sufficient conditions to ensure the global uniform exponential stability of the closed-loop PDT SPSSs are derived. Based on the aforementioned conditions, the analyses of the extended dissipative performance of the closed-loop PDT SPSSs and a preferable decoupling method deriving the mode-dependent controller gains are given for the first time. Finally, the potential practicability of the method is verified by a purely numerical example and a tunnel diode circuit model, and a convex optimization method calculating the upper bound of the singular perturbation parameter is provided.

Variability-Aware Modeling of Filamentary Oxide-Based Bipolar Resistive Switching Cells Using SPICE Level Compact Models

Abstract: Bipolar resistive switching (BRS) cells based on the valence change mechanism show great potential to enable the design of future non-volatile memory, logic and neuromorphic circuits and architectures. To study these circuits and architectures, accurate compact models are needed, which showcase the most important physical characteristics and lead to their specific experimental behavior. If BRS cells are to be used for computation-in-memory or for neuromorphic computing, their dynamical behavior has to be modeled with special consideration of switching times in SET and RESET. For any realistic assessment, variability has to be considered additionally. This study shows that by extending an existing compact model, which by itself is able to reproduce many different experiments on device behavior critical for the anticipated device purposes, variability found in experimental measurements can be reproduced for important device characteristics such as I-V characteristics, endurance behavior and most significantly the SET and RESET kinetics. Furthermore, this enables the study of spatial and temporal variability and its impact on the circuit and system level.

Adaptive Fuzzy Output Feedback Event-Triggered Control for a Class of Switched Nonlinear Systems With Sensor Failures

Abstract: This paper investigates the adaptive fuzzy output feedback event-triggered control problem for a class of switched nonlinear systems with sensor faults. Due to that the unknown nonlinearities of the systems are more general and the sensor undergoes faults, the considered problem is difficult to be addressed by existing schemes. Therefore, fuzzy logic systems are employed to approximate unknown nonlinear terms and a fault compensation coefficient is introduced to compensate for the effect of sensor failures. Then, a state observer is established for estimating unmeasured states. By choosing a suitable common Lyapunov function, an adaptive fuzzy output feedback fault-tolerant event-triggered controller is derived. It is proven that the proposed scheme can guarantee that the system output tracks the desired trajectory effectively, all states of the resulting closed-loop system are semi-globally uniformly ultimately bounded, and the Zeno phenomenon is excluded. Finally, two simulation examples, which include a switched RLC circuit system and a numerical example, are presented to show the the effectiveness of the proposed strategy.

Weight-Oriented Approximation for Energy-Efficient Neural Network Inference Accelerators

Abstract: Current research in the area of Neural Networks (NN) has resulted in performance advancements for a variety of complex problems. Especially, embedded system applications rely more and more on the utilization of convolutional NNs to provide services such as image/audio classification and object detection. The core arithmetic computation performed during NN inference is the multiply-accumulate (MAC) operation. In order to meet tighter and tighter throughput constraints, NN accelerators integrate thousands of MAC units resulting in a significant increase in power consumption. Approximate computing is established as a design alternative to improve the efficiency of computing systems by trading computational accuracy for high energy savings. In this work, we bring approximate computing principles and NN inference together by designing NN specific approximate multipliers that feature multiple accuracy levels at run-time. We propose a time-efficient automated framework for mapping the NN weights to the accuracy levels of the approximate reconfigurable accelerator. The proposed weight-oriented approximation mapping is able to satisfy tight accuracy loss thresholds, while significantly reducing energy consumption without any need for intensive NN retraining. Our approach is evaluated against several NNs demonstrating that it delivers high energy savings (17.8% on average) with a minimal loss in inference accuracy (0.5%).

ADP-Based Security Decentralized Sliding Mode Control for Partially Unknown Large-Scale Systems Under Injection Attacks

Abstract: In this paper, the decentralized optimal control problem is addressed for a class of large-scale systems subject to injection attacks. All subsystem matrices are considered to be unavailable to the designer. A model-free decentralized sliding mode control (SMC) scheme for each subsystem is designed via just utilizing its own state information and the known bounds of the interconnections and the injection attacks. Moreover, the adaptive dynamic programming (ADP) approach is incorporated to deal with the infinite horizon optimal control problem for the sliding mode dynamics, which is equivalent to the solution of a set of parallel algebraic Riccati equations. Furthermore, a novel parallel policy iteration algorithm is developed to implement the proposed decentralized SMC scheme without using all subsystems dynamics matrices. Specifically, it is shown that during the whole policy iteration steps, the reachability of each sliding variable and the stability of each sliding mode dynamics are guaranteed simultaneously by the online updating decentralized SMC scheme. Finally, the applicability of the proposed novel ADP-based decentralized SMC strategy is illustrated by a two-machine power system subject to three different injection attacks.

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor

Abstract: This paper proposes a high power-performance-area efficient background noise aware keyword-spotting (KWS) processor based on an optimized binarized weight network (BWN). To reduce the power consumption while maintaining the system recognition accuracy for different background noise, the KWS processor with a SNR prediction module can be adaptively configured to use dual computing modes (standard computing mode and approximate computing mode) for both high recognition accuracy under high background noise and ultra-low power consumption under low background noise. The mel-scale frequency cepstral coefficients (MFCC) module is optimized with approximate computing technologies, which can reduce the power consumption by up to $3.1\times $ and $5.7\times $ for high/low background noise, respectively. Based on the evaluation of the architecture design space exploration, an ultra-low power BWN accelerator with low voltage, area and leakage power and using precision self-adaptive approximate computing units was proposed. Evaluated under 22nm process technology, this work can support up to 10 keywords real time recognition with power consumption of $15.1~\mu \text{W}$ for high background noise and $10.8~\mu \text{W}$ for low background noise. Compared to the state-of-the-art KWS architectures, our work can achieve ultra-low power consumption (about $1.7\times $ reduced), while maintaining high system capability and adaptability.

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

Abstract: In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC) model is integrated and solved self-consistently within the BSIM-CMG model. This allows the creation of NC-FinFET standard cell libraries, while considering the effects of various variability sources both in the ferroelectric layer as well as in the underlying constituent FinFET device. The variability-aware NC-FinFET libraries, fully compatible with the existing standard design flow of circuits, are then employed to perform simulations using commercial statistical timing analysis tools in order to study the performance of a 14nm processor. For comprehensive analysis and comparisons, our implementation is done for both NC-FinFET and conventional (baseline) FinFET for a wide range of voltages. Our results demonstrate that process variations have a larger impact on the processor’s performance in NC-FinFET – when it operates at a lower voltage compared to the baseline FinFET that still operates at the nominal high voltage – due to the additional ferroelectric-induced variability. Results also reveal that neglecting process variations leads to overestimating the benefit that NC brings to the processor’s frequency improvement because of the larger timing guardband that is needed to overcome variability in NC-FinFET.

Probabilistic-Constrained Distributed Filtering for a Class of Nonlinear Stochastic Systems Subject to Periodic DoS Attacks

Abstract: This paper investigates the probabilistic-constrained distributed filtering problem for a class of nonlinear stochastic systems with state constraints and cyber attacks. The considered cyber attacks are periodic denial-of-service (DoS) attacks which are modeled by a kind of periodic pulse-width-modulated (PWM) jamming signals. Different from some existing works, by using the proposed filter design method, the probability of the filtering error exceeding a threshold can be guaranteed below a certain level quantitatively. Furthermore, in order to economize the limited bandwidth resources, an event-triggered communication scheme (ETS) is designed for the data transmission. The aim of the problem addressed is to design a time-varying distributed filters such that: 1) the probability of the filtering error restricted to a given ellipsoid is larger than a specified value; and 2) the obtained ellipsoid threshold is minimized in the sense of matrix norm at each time point. To achieve this purpose, a recursive linear matrix inequality method is utilized and sufficient conditions are derived. Moreover, the filter parameters are explicitly determined in terms of the solution to certain matrix inequalities. Finally, the reliability and applicability of the proposed distributed filtering strategy are demonstrated by an illustrative example.

Machine Learning-Based Approach for Hardware Faults Prediction

Abstract: Hardware failures are undesired but a common problem in circuits. Such failures are inherently due to the aging of circuitry or variation in circumstances. In critical systems, customers demand the system never to fail. Several self-healing and fault tolerance techniques have been proposed in the literature for recovering a circuitry from a fault. Such techniques come to the rescue when a fault has already occurred but they are typically uninformed about the possibility of an impending failure (i.e., fault prediction), which can be used as a pre-stage to fault tolerance and self-healing. This paper presents an approach to early fault prediction of circuits. The proposed method uses Fast Fourier Transform (FFT) to get the fault frequency signature, Principal Component Analysis (PCA) to get the most important data with reduced dimension, and Convolutional Neural Network (CNN) to learn and classify the fault. The proposed method is validated for working in different circuits by testing it using two circuits: comparator and amplifier. The comparator and amplifier are implemented using 45 nm technology on HSPICE to extract the failures dataset in terms of voltage, current, temperature, noise, and delay. This extracted data is used for training the proposed approach using Tensorflow. To the best of our knowledge, this is the first work of fault prediction at the transistor level for hardware system. The proposed approach considers aging, short-circuit, and open-circuit faults, and it provides a fault prediction accuracy of 98.93% and 98.91% for comparator and amplifier circuits, respectively. The proposed method is tested for two different circuits for its validation, and it consumes 1.08 W for Altera Arria 10 GX FPGA device.

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets

Abstract: The continuous advancement of CMOS technologies makes SRAMs more and more sensitive to soft errors. This paper presents two novel radiation-hardened SRAM cell designs, namely S4P8N and S8P4N, with enhanced self-recoverability from single-node upsets (SNUs) and Double-node upsets (DNUs). First, the S4P8N cell that has more redundant nodes and more access transistors is proposed. The cell has the following advantages: (1) it can self-recover from all possible SNUs; (2) it can self-recover from a part of DNUs; (3) it has small overhead in terms of power dissipation. Then, to reduce read and write access time, the S8P4N cell that uses a special feedback mechanism among its internal nodes is proposed. The cell has similar soft error tolerability as the S4P8N cell. Simulation results validate the high robustness of the proposed SRAM cells. These results also show that the write access time, read access time, and power dissipation of the S8P4N cell are reduced approximately by 29%, 20%, and 21% on average, at the cost of moderate silicon area, when compared with the state-of-the-art radiation-hardened SRAM cells.

Advanced Control Strategies for DC–DC Buck Converters With Parametric Uncertainties via Experimental Evaluation

Abstract: In this paper, four control strategies for DC-DC buck converters are proposed, compared and analyzed: a single-loop adaptive control strategy (SA), a double-loop adaptive control strategy (DA), a single-loop disturbance observer-based control strategy (SDOB) and a double-loop disturbance observer-based control strategy (DDOB). First, the nominal system without considering the parametric uncertainties of the DC-DC buck converter is built to help develop the SA and DA. The SA is built by adaptive and backstepping control approaches, and the DA is set up by adaptive and sliding mode control approaches. Additionally, a model considering parametric uncertainties is introduced, giving the opportunity to develop the SDOB and DDOB. The SDOB is developed using a designed disturbance observer and backstepping control technique, and the DDOB is synthesized using a designed disturbance observer and sliding mode control method. Finally, the advantages and disadvantages of the four proposed control strategies are compared and analyzed through experiments.

A Transient-Enhanced Output-Capacitorless LDO With Fast Local Loop and Overshoot Detection

Abstract: An output-capacitorless low-dropout regulator (OCL-LDO) with simple structure and fast transient response is proposed for system-on-chip (SoC) applications. A super source follower is inserted into a cascoded flipped voltage follower to drive the power transistor, which forms a fast-local loop for quick turn-on. A robust overshoot detection circuit consuming only leakage current is proposed for fast turn-off. The combination of these two techniques significantly reduce the overshoot/undershoot voltages and achieve fast settling time during load steps. A simple yet effective additional turn-around stage is added in the error amplifier to improve the positive phase slew rate for potential dynamic voltage scaling (DVS) function in battery-operated systems. The LDO is implemented in a 65 nm CMOS process and it can deliver a 20 mA load current with 0.9 V regulated output and 150 mV dropout voltage. It occupies an active area of 0.01 mm $^{\mathbf {2}}$ and can work stably in a load range from 0 to 20 mA with $65~\mu \text{A}$ quiescent current. The measured results show a settling time about 100 ns for load steps from $100~\mu $ A to 20 mA as well as V $_{\mathbf {REF}}$ and V $_{\mathbf {IN}}$ steps.

Pinning-Observer-Based Secure Synchronization Control for Complex Dynamical Networks Subject to DoS Attacks

Abstract: Under the framework of cyber-physical systems (CPSs), this paper is concentrated on the secure synchronization control problem for complex dynamical networks subject to denial-of-service (DoS) attacks. The so-called pinning-nodes-based observer, which only utilizes the measurement outputs of pinning nodes, is designed to estimate all system states. Different from the existing studies where the network environment is secure, intermittent DoS attacks are considered here in the measurement (sensor-to-controller) and control (controller-to-actuator) channels. These two channels will be blocked by DoS attacks when the attacker being active. By the theories of Lyapunov and comparison, the secure synchronization scheme for the considered system under intermittent DoS attacks is given. Finally, a numerical example is exhibited to confirm the availability of the developed theoretical outcomes.

Decentralized Adaptive Event-Triggered Control for a Class of Uncertain Systems With Deception Attacks and Its Application to Electronic Circuits

Abstract: The problem of decentralized event-triggered control for a class of network-based state-dependent uncertain systems subject to network transmission delay and deception attacks is considered in this article. To reduce network load, a novel decentralized adaptive event-triggered scheme (AETS) is developed to transmit necessary sampled signals. During network transmission, a more practical deception attack phenomenon is considered, where the attack behaviors in different channels are governed by independent Bernoulli processes. Moreover, a set of improved data buffers are applied in the controller side to organize the decentralized triggered data and alleviate the impact of network transmission delay, such that the transmitted data can be utilized timely. Then, an integrated closed-loop system with state-dependent uncertainties is constructed by taking the AETS, deception attacks and data buffers into account. Sufficient conditions that guarantee the mean-square exponential stability of the closed-loop system are presented by employing the Lyapunov functional method, and the design criterion of the controller gain is given by an exact expression. Finally, the proposed method is applied to the control of electronic circuits to verify its practicability and effectiveness.

SIKE’d Up: Fast Hardware Architectures for Supersingular Isogeny Key Encapsulation

Abstract: In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA’s, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST’s post-quantum standardization process.

Beamspace Channel Estimation for Massive MIMO mmWave Systems: Algorithm and VLSI Design

Abstract: Millimeter-wave (mmWave) communication in combination with massive multiuser multiple-input multiple-output (MU-MIMO) enables high-bandwidth data transmission to multiple users in the same time-frequency resource. The strong path loss of wave propagation at such high frequencies necessitates accurate channel state information to ensure reliable data transmission. We propose a novel channel estimation algorithm called BEAmspace CHannel EStimation (BEACHES), which leverages the fact that wave propagation at mmWave frequencies is predominantly directional. BEACHES adaptively denoises the channel vectors in the beamspace domain using an adaptive shrinkage procedure that relies on Stein’s unbiased risk estimator (SURE). Simulation results for line-of-sight (LoS) and non-LoS mmWave channels reveal that BEACHES performs on par with state-of-the-art channel estimation methods while requiring orders-of-magnitude lower complexity. To demonstrate the effectiveness of BEACHES in practice, we develop a very large-scale integration (VLSI) architecture and provide field-programmable gate array (FPGA) implementation results. Our results show that adaptive channel denoising can be performed at high throughput and in a hardware-friendly manner for massive MU-MIMO mmWave systems with hundreds of antennas.

Robust H ∞ Pinning Synchronization for Complex Networks With Event-Triggered Communication Scheme

Abstract: This paper investigates the issue of global robust ${H_\infty }$ pinning synchronization for a class of complex networks with sampled-data-based event-triggered communication via a pinning control approach. The complex network is subject to network-induced time-varying delays, parametric uncertainties and external disturbances. A directed and weighted communication topology is taken into account, and the phenomenon of uncertainties is reflected in both modelling and inner coupling matrices. In order to save communication resources, a new and practical event-triggered communication mechanism with an asynchronous sampling manner is developed, with which the Zeno behaviour can be absolutely avoided. Then, based on the presented event-triggered strategy, a pinning control protocol is proposed to reduce the frequency of controller updates and the computational burden. The problems on the minimal number and which of the nodes should be chosen are addressed. By Lyapunov stability theory, sufficient conditions are deduced to ensure the underlying network achieves global robust ${H_\infty }$ pinning synchronization. Finally, numerical examples are provided to verify the effectiveness of the new design techniques.

Incremental Delta-Sigma ADCs: A Tutorial Review

Abstract: In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

S-Type Locally Active Memristor-Based Periodic and Chaotic Oscillators

Abstract: S-type locally-active memristor (LAM) has a great potential for brain- inspired neuromorphic computing, where the S-type LAM-based oscillator is a fundamental building block. Concerning the S-type LAM, this paper constructs a material-independent model in simple mathematical expression, which can be relatively easily analyzed. By biasing the memristor into the locally- active region, and connecting it with a capacitor, a second-order oscillator can be built. The small-signal equivalent circuit of the memristor and its frequency response are applied to determine the period oscillation frequency range and compensation capacitance. Hopf bifurcation theory is used to analyze oscillation mechanism of the second-order circuit and appropriate capacitance. By adding an extra inductor into the second-order oscillator, a novel third-order chaotic circuit is developed, where a saddle-focus is derived to create chaos. Its dynamic characteristics are investigated via Lyapunov exponents, bifurcation diagrams, dynamic route map, and so on. The local activities of the single memristor, second-order oscillator, and third-order chaotic circuit are verified through the mathematical analysis. Finally, physical circuit realizations of the S- type LAM-based oscillators, including the memristor emulator, are presented. Both simulation and experimental results demonstrate the practicability of the proposed mathematical model and the validity of the theoretical analysis.

Exploiting Sensitivity Enhancement in Micro-wave Planar Sensors Using Intermodulation Products With Phase Noise Analysis

Abstract: In this paper, a new technique to enhance the sensitivity of microwave resonators is introduced Double split ring resonators are implemented as the core of a loss-compensated resonator It is illustrated that regenerative oscillators when mixed together can produce higher order intermodulation products (IMP) at the output The variations in sensing tone are multiplied and exhibit considerably higher sensitivities at 3rd, 5th, and 7th IMP components compared to the main resonant frequency The sensor is also integrated into wireless platform with ultra-wideband bowtie antennas Common fluids such as Toluene, n-Heptane, IPA, Ethanol, Methanol, Acetone, and Water are tested in fluidic channel and demonstrated that the sensitivity for intermodulation products are significantly increased proportional to the order of IMP The proposed sensor is also examined with glucose concentration sensing for the range of 0– 600 mg/dL and significant variation for 7th IMP sensor is observed as opposed to saturation of conventional sensor Also, asphaltene concentrations down to 6 ppm are recognizable when precipitated from toluene solution using the proposed sensor Moreover, a rigorous analytical study is presented for phase noise of the IMP originated from reference signals

A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM

Abstract: A millimeter-wave current-reuse voltage-controlled oscillator (VCO) features a single-turn multi-tap inductor and two separate differential-only switched-capacitor arrays to improve the power efficiency and phase noise (PN). Specifically, a single-branch complementary VCO topology, in conjunction with a multi-resonant Resistor-Inductor-Capacitor-Mutual inductance (RLCM) tank, allows sharing the bias current and reshaping the impulse-sensitivity-function. The latter is based on an area- efficient RLCM tank to concurrently generate two high quality- factor differential-mode resonances at the fundamental and 2nd- harmonic oscillation frequencies. Fabricated in 65-nm CMOS technology, our VCO at 27.7 GHz shows a PN of −109.91-dBc/Hz at 1-MHz offset (after on-chip divider-by-2), while consuming just 3.3 mW at a 1.1-V supply. It corresponds to a Figure-of-Merit (FOM) of 187.6 dBc/Hz. The frequency tuning range is 15.3% (25.2 to 29.4 GHz) and the core area is 0.116 mm2.

Distributed Fixed-Time Triggering-Based Containment Control for Networked Nonlinear Agents Under Directed Graphs

Abstract: This paper discusses the distributed fixed-time containment control for networked nonlinear systems via the event/self-triggered approaches over directed graphs. A distributed event-triggered control protocol without continuous control updates is first proposed. In order to relieve the chattering effect, a modified distributed event-triggered control law is developed. To further overcome the drawback of continuous state monitoring and reduce the communication frequency between neighboring agents, a distributed chattering-free self-triggered control strategy is accordingly designed. A favorable aspect of our work is that the unnecessary resource utilizations of computation, communication as well as control updates can be saved while sustaining the desired control properties and excluding the Zeno behavior. Another distinct feature of this paper lies in that the containment control objective is realized in fixed time and the estimate of settling time can be prescribed without dependence on initial states of networked agents. Finally, some simulation results are provided to illustrate the effectiveness of the theoretical control schemes.

Distributed Model Predictive Consensus of Heterogeneous Time-Varying Multi-Agent Systems: With and Without Self-Triggered Mechanism

Abstract: This paper provides a framework of designing distributed model predictive controller to reach consensus of a heterogeneous time-varying multi-agent system, and the dynamics of heterogeneous agents are modeled by double integrators and Euler-Lagrange (EL) equations. Firstly, a DMPC-based consensus algorithm is proposed, where the constraints in the algorithm depend on the heterogeneous dynamics. We prove that the resultant DMPC optimization problem is feasible with the designed controllers, which is stable when the system reaches consensus. To further reduce communication cost and solve the problem with asynchronous discrete-time information exchange, self-triggered mechanism is introduced into the framework. Trigger intervals are alternatively optimized with the control inputs, and the influence on the system performance is analyzed. Numerical examples are provided to verify the effectiveness and advantages of the proposed algorithms.

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR

Abstract: An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB $\Omega $ , and 4.68 pA/ $\surd $ Hz respectively. The proposed AFE circuit, which is fabricated in $0.18~\mu \text{m}$ CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications

Abstract: Ultra-low-power circuits that can work under a low-voltage supply are in great demand in future wearable biomedical applications, which tend to be integrated with low-output-voltage energy harvesting devices. In this paper, we present a low-voltage low-power continuous-time low-pass filter (CT-LPF), which is indispensable in biomedical systems. When a low-voltage supply is used, it is necessary to make the output quiescent voltage ( $\text{V}_{\mathrm {Q}}$ ) stable in the LPF, otherwise the dynamic range will be reduced. Conventional Source-follower (SF) based topologies can achieve ultra-low-power consumption. However, the difference of the input and output $\text{V}_{\mathrm {Q}}$ is sensitive to process and temperature variations. In this work, a complementary SF based topology with a bulk-common-mode-feedback (B-CMFB) circuit is proposed to keep the output $\text{V}_{\mathrm {Q}}$ tracking the input $\text{V}_{\mathrm {Q}}$ and immune to the process and temperature variations. A 4th-order LPF using the proposed topology has been implemented in a standard $0.18~\mu \text{m}$ CMOS process, which achieves a power consumption of only 3.69-nW under a 0.5-V voltage supply with a bandwidth of 200 Hz. Measurement results show that the input-referred noise is $91.9~\mu \text{V}_{\mathrm {rms}}$ . The IIP3 is 5.0 dBm and the dynamic range (DR) is 48.5 dB. The active chip area is only 0.074 mm2. The proposed LPF achieves both ultra-low power consumption with a 0.5-V supply and a stable output $\text{V}_{\mathrm {Q}}$ immune to process and temperature variations, which is suitable for low-supply-voltage biomedical systems.

Double-Sub-Stream M-ary Differential Chaos Shift Keying Wireless Communication System Using Chaotic Shape-Forming Filter

Abstract: An M-ary Differential Chaos Shift Keying modulation using Chaotic Shape-forming Filter (CSF-M-DCSK) is proposed here to transmit two sub-streams with different system performances. The chaotic shape-forming filter is used to generate the chaotic carrier which is modulated according to the DCSK concept. The modulated chaotic signal is demodulated by a coherent matched filter receiver and the maximum likelihood decision rule is used to get the best noise performance. Compared to DCSK and its enhanced versions, the new modulation scheme offers not only better noise and multipath performances but also a higher data rate. The hardware implementation of the proposed method is as simple as that of a conventional communication system. Analytical expressions have been derived for the CSF-M-DCSK Bit Error Rate (BER) and its performance has been evaluated in AWGN and multipath channels by simulations. The new CSF-M-DCSK system has been implemented and successfully tested on a Wireless open-Access Research Platform (WARP). Results of simulations and measurements performed in real application scenarios have proven the feasibility and superiority of CSF-M-DCSK over its competitors.

Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization

Abstract: Modern communication standards, such as 5G new radio (5G NR), require a high speed decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely used approach in QC-LDPC decoders is a layered decoding schedule which processes the parity check matrix in parts, thus providing faster convergence. However, pipelined layered decoding architecture suffers from data hazards that reduce the throughput. This paper presents a novel architecture, which can facilitate any QC-LDPC decoding without stall cycles caused by pipeline hazards. The decoder conveniently incorporates both the layered and the flooding schedules in cases when hazards occur. The paper also presents the genetic algorithm based optimization of the decoding schedule for better signal-to-noise ratio (SNR) performance. The proposed architecture enables insertion of a large number of pipeline stages, thus providing high operating frequency. As a case study, the FPGA implementation for WiMAX, DVB-S2X, and 5G NR provided coded throughput of up to 1.77 Gbps, 4.32 Gbps, and 4.92 Gbps at 10 iterations, respectively. The results show a strong throughput increase of 30%–109% compared with the conventional layered decoder for 5G NR for the same SNR performance. The decoder provides highly efficient utilization of resources when compared with the state-of-the-art solutions.

Fault-Tolerant Control Based on Virtual Actuator and Sensor for Discrete-Time Descriptor Systems

Abstract: This article proposes a fault-tolerant control (FTC) strategy based on virtual actuator and sensor for discrete-time descriptor systems subject to actuator and sensor faults. The fault-tolerant closed-loop system, which includes the nominal controller and observer, as well as the virtual actuator and the virtual sensor, hides the effects of faults. When an observer-based state-feedback law is considered, the existence of algebraic loop may prevent the practical implementation due to the current algebraic states depending on the current control input, that affects also the implementation of the virtual actuator/sensor. To deal with this issue, an observer-based delayed feedback controller and a delayed virtual actuator are proposed for discrete-time descriptor systems. Furthermore, the satisfaction of the separation principle is shown, and an improved admissibility condition is developed for the design of the controller and virtual actuator/sensor. Finally, some simulation results including an electrical circuit are used to demonstrate the applicability of the proposed methods.

Output Regulation for Switched Systems With Multiple Disturbances

Abstract: This article aims at proposing a regulation anti-disturbance control scheme for switched systems encountered by multiple disturbances, including the measurable disturbance and unmeasurable disturbance, through a multiple Lyapunov functions method. A switched estimator is developed for estimating the unmeasurable disturbance, under which a switched regulator and a switching law are co-designed to regulate the system output, while resisting the influence of the disturbances on the switched systems. Sufficient conditions are provided to ensure the output regulation performance and the disturbance restrain performance for the switched systems, even if all subsystems may not have the performances. These conditions are also appropriate for non-switched systems. By applying the established regulation anti-disturbance control method to the regulation of the speed for an engine model, the validity of the control scheme is displayed.

Automated Deep Neural Learning-Based Optimization for High Performance High Power Amplifier Designs

Abstract: This study presents an automated optimization-oriented strategy for designing high power amplifiers (HPAs) using deep neural networks (DNNs). The proposed strategy consists of two optimization phases that are applied sequentially. In the first phase, the circuit topology is optimized by determining the number of passive components in the input and output matching networks using deep learning classification network. In the second optimization phase, component values are estimated using a deep learning regression network with electromagnetic-based Thompson Sampling Efficient Multiobjective Optimization (TSEMO). The proposed approach is compact, in the sense that the optimum solution is automatically generated by the process, opposite to the conventional approaches where manual post-processing is required to prune the process outcomes. It addresses the problem of heavy reliance of the system performance on the designer’s experience and automatically generates valid layouts. In the demanding HPA design problem, uses of DNNs have been shown to provide much more accuracy than conventional shallow neural networks. The effectiveness of the proposed method is verified by implementing two designed HPAs, including GaN HEMTs. The efficiency-oriented optimized amplifier reveals higher than 60% drain efficiency, and the gain-oriented optimized amplifier has 17.6–18 dB linear gain in the frequency band of 1.8–2.2 GHz.