Journal ArticleDOI
A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator
Lakshmi Kanta Bera,M. Mukherjee-Roy,B. Abidha,Ajay Agarwal,W.Y. Loh,C.H. Tung,Rakesh Kumar,A. D. Trigg,Y. L. Foo,Sukant K. Tripathy,G. Q. Lo,N. Balasubramanian,Dim-Lee Kwong +12 more
TLDR
In this paper, a tensile-strained Si n-MOSFET and compressive strained-SiGe p-MosFET were integrated on an Si/SiGe-on-insulator (SOI) substrate, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state).Abstract:
This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (/spl epsiv//spl sim/ -1.07%) strained- Si/sub 0.55/Ge/sub 0.45/ and the n-MOSFET in tensile-strained Si over the relaxed Si/sub 0.80/Ge/sub 0.20/ exhibited significant hole (enhancement factor /spl sim/ 1.9) and electron (enhancement factor /spl sim/ 1.6) mobility enhancements over the Si reference.read more
Citations
More filters
Patent
Process for forming an electronic device including a transistor having a metal gate electrode
TL;DR: In this article, the first and second gate electrodes having the same minority carrier type are associated with the first-and second-gate electrodes, respectively, for the n-channel and p-channel transistor, respectively.
Patent
Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium
TL;DR: In this paper, a method for producing a microelectronic device including a plurality of Si 1-y Ge y based semi-conducting zones (where 0
Journal ArticleDOI
Experimental Investigation of Hole Transport in Strained $\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{SOI}$ pMOSFETs—Part I: Scattering Mechanisms in Long-Channel Devices
TL;DR: In this paper, a wide experimental study of hole transport in SiGe pMOSFETs was presented, where various Ge contents, from 20% up to 60%, and growth templates [unstrained or tensely strained silicon-on-insulator (SOI)] were screened in order to study the influence of various strain levels and Ge concentrations.
Book ChapterDOI
Comparing CMOS-Based and NEMS-Based adiabatic logic circuits
TL;DR: In this paper, a detailed comparison between the expected performance of CMOS-based and nanoelectromechanical systems (NEMS) based adiabatic logic circuits is presented.
Patent
Strained thin body semiconductor-on-insulator substrate and device
TL;DR: In this article, an active device layer is formed over the second semiconductor layer such that the active device semiconductor layers are initially in a relaxed state and one or more trench isolation structures are formed through both active device and active device layers.
References
More filters
Journal ArticleDOI
Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors
TL;DR: In this paper, the authors investigated the phonon-limited mobility of strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) through theoretical calculations including two-dimensional quantization.
Journal ArticleDOI
Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors
TL;DR: In this article, n-type metal-oxide-semiconductor field effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si/sub 1/spl minus/x/Ge/sub x/ standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si Similar enhancements are observed in the device transconductance
Electron Mobility Enhancement in S trained-Si N-Type Metal-Oxide- S emiconductor Field-Effect Transistors
TL;DR: In this paper, n-type metal-oxide-semiconductor field effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si1 -zGez were used.
Journal ArticleDOI
Subband structure and mobility of two-dimensional holes in strained Si/SiGe MOSFET’s
R. Oberhuber,G. Zandler,P. Vogl +2 more
TL;DR: In this paper, the hole mobility of a strained Si metal-oxide-semiconductor field effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated theoretically and compared with the mobility of conventional (unstrained) Si $p$-MOSFLT's.
Proceedings ArticleDOI
Strained silicon MOSFET technology
J.L. Hoyt,Hasan M. Nayfeh,Satoshi Eguchi,Ingvar Åberg,Guangrui Xia,T. S. Drake,Eugene A. Fitzgerald,Dimitri A. Antoniadis +7 more
TL;DR: In this article, electron mobility enhancements at high channel doping (up to 6 /spl times/ 10/sup 18/ cm/sup -3/) are characterized in strained Si n-MOSFETs for low inversion layer carrier concentrations, channel-dopant ionized impurity scattering does reduce the strain-induced mobility enhancement, but the enhancement is recovered at higher inversion charge concentrations, where screening is efficient.