Showing papers on "Dopant Activation published in 2014"

Direct imaging of p-n junction in core-shell GaN wires.

Abstract: While core–shell wire-based devices offer a promising path toward improved optoelectronic applications, their development is hampered by the present uncertainty about essential semiconductor properties along the three-dimensional (3D) buried p–n junction. Thanks to a cross-sectional approach, scanning electron beam probing techniques were employed here to obtain a nanoscale spatially resolved analysis of GaN core–shell wire p–n junctions grown by catalyst-free metal–organic vapor phase epitaxy on GaN and Si substrates. Both electron beam induced current (EBIC) and secondary electron voltage constrast (VC) were demonstrated to delineate the radial and axial junction existing in the 3D structure. The Mg dopant activation process in p-GaN shell was dynamically controlled by the ebeam exposure conditions and visualized thanks to EBIC mapping. EBIC measurements were shown to yield local minority carrier/exciton diffusion lengths on the p-side (∼57 nm) and the n-side (∼15 nm) as well as depletion width in the r...

Controlled doping of silicon nanocrystals investigated by solution-processed field effect transistors.

Abstract: The doping of semiconductor nanocrystals (NCs), which is vital for the optimization of NC-based devices, remains a significant challenge. While gas-phase plasma approaches have been successful in incorporating dopant atoms into NCs, little is known about their electronic activation. Here, we investigate the electronic properties of doped silicon NC thin films cast from solution by field effect transistor analysis. We find that, analogous to bulk silicon, boron and phosphorus electronically dope Si NC thin films; however, the dopant activation efficiency is only ∼10–2–10–4. We also show that surface doping of Si NCs is an effective way to alter the carrier concentrations in Si NC films.

Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI

Abstract: Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching. The channel length, defined as the width of the V-groove bottom, was as short as 3 nm, and the channel thickness was between 1 and 8 nm. Excellent transistor characteristics with threshold voltages that are optimal for low-power operation were obtained for both n-FETs and p-FETs when the thickness of both the channel and gate dielectric film thickness was reduced to 1 nm. The origin of the excellent electrostatic control is discussed on the basis of fringe capacitance and quantum confinement effects in a nanometer-scale ultrathin Si layer where band-gap expansion, dielectric constant reduction, and increase in the dopant activation energy become prominent. The electrical characteristics of the ultrashort channel JL-FETs were found to be very sensitive to device parameters such as the channel thickness and dopant concentration.

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Abstract: Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

Optimized Laser Thermal Annealing on Germanium for High Dopant Activation and Low Leakage Current

Abstract: In this paper, state-of-the-art laser thermal annealing is used to fabricate Ge diodes. We compared the effect of laser thermal annealing (LTA) and rapid thermal annealing (RTA) on dopant activation and electrical properties of phosphorus and Arsenic-doped n+/p junctions. Using LTA, high carrier concentration above 10 20 cm -3 was achieved in n-type doped regions, which enables low access resistance in Ge devices. Furthermore, the LTA process was optimized to achieve a diode I ON /I OFF ratio ~10 5 and ideality factor (n) ~1.2, as it allows excellent junction depth control when combined with optimized implant conditions. On the other hand, RTA revealed very high I ON /I OFF ratio ~10 7 and n ~1, at the cost of high dopant diffusion and lower carrier concentrations which would degrade scalability and access resistance.

High Performance 400 °C p + /n Ge Junctions Using Cryogenic Boron Implantation

Abstract: We report high performance Ge p + /n junctions using a single, cryogenic (-100 °C) boron ion implantation process. High activation>4 × 10 20 cm -3 results in specific contact resistivity of 1.7 × 10 -8 Ω-cm 2 on p + -Ge, which is close to ITRS 15 nm specification (1 × 10 -8 Ω-cm 2 ) and nearly 4.5× lower than the state of the art (8 × 10 -8 Ω-cm 2 ). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p + /n junctions can pave the way for future high mobility Ge p-MOSFETs.

Subsecond annealing of advanced materials : annealing by lasers, flash lamps and swift heavy ions

Abstract: The very early time.- Nanonet formation by constitutional supercooling of pulsed laser annealed, Mn-implanted germanium.- Metastable activation of dopants by solid phase epitaxial recrystallization.- Superconducting Ga-implanted Germanium.- Structural changes in SiGe/Si layers induced by fast crystallization.- Sub-nanosecond thermal spike-induced nanostructuring of thin solid films under swift heavy-ion (SHI) irradiation.- Pulsed-laser-induced epitaxial growth of silicon for three-dimensional integrated circuits.- Improvement of performance and cost of functional films using large area laser RTP.- Pulsed laser dopant activation for semiconductors and solar cells.- Formation of high-quality m-order-thick poly-Si films on glass substrates by flash lamp annealing.- Millisecond-range liquid-phase processing of silicon-based hetero-nanostructures.- Radiation thermometry - sources of uncertainty during contactless temperature measurement.- Millisecond annealing for semiconductor device applications.- Low-cost and large-area electronics, roll-to-roll processing and beyond.- Application of sub-second annealing for dilute ferromagnetic semiconductors.

Kinetic Monte Carlo simulations of boron activation in implanted Si under laser thermal annealing

Abstract: We investigate the correlation between dopant activation and damage evolution in boron-implanted silicon under excimer laser irradiation The dopant activation efficiency in the solid phase was measured under a wide range of irradiation conditions and simulated using coupled phase-field and kinetic Monte Carlo models With the inclusion of dopant atoms, the presented code extends the capabilities of a previous version, allowing its definitive validation by means of detailed comparisons with experimental data The stochastic method predicts the post-implant kinetics of the defect-dopant system in the far-from-equilibrium conditions caused by laser irradiation The simulations explain the dopant activation dynamics and demonstrate that the competitive dopant-defect kinetics during the first laser annealing treatment dominates the activation phenomenon, stabilizing the system against additional laser irradiation steps

Study on electrical properties of metal/GaSb junctions using metal-GaSb alloys

Abstract: We study the metal-GaSb alloy formation, the structural properties and the electrical characteristics of the metal-alloy/GaSb diodes by employing metal materials such as Ni, Pd, Co, Ti, Al, and Ta, in order to clarify metals suitable for GaSb p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) as metal-GaSb alloy source/drain (S/D). It is found that Ni, Pd, Co, and Ti can form alloy with GaSb by rapid thermal annealing at 250, 250, 350, and 450 °C, respectively. The Ni-GaSb and Pd-GaSb alloy formation temperature of 250 °C is lower than the conventional dopant activation annealing for ion implantation, which enable us to lower the process temperature. The alloy layers show lower sheet resistance (RSheet) than that of p+-GaSb layer formed by ion implantation and activation annealing. We also study the electrical characteristics of the metal-alloy/GaSb junctions. The alloy/n-GaSb contact has large Schottky barrier height (ϕB) for electrons, ∼0.6 eV, and low ϕB for holes, ∼0.2 eV, which e...

Raman spectroscopy studies of dopant activation and free electron density of In0.53Ga0.47As via sulfur monolayer doping

Abstract: We present a Raman spectroscopy study of electron–phonon coupling in In0.53Ga0.47As epilayers doped via the sulfur-monolayer doping method. A high-frequency coupled mode (HFCM) detected above 400 cm−1 shifts with increasing charge carrier density and allows for extraction of the activated dopant concentrations.

High performance triangular barrier engineered NIPIN selector for bipolar RRAM

Abstract: Triangular barrier has been proposed and implemented for the first time in a punch-through diode based selector by dopant profile engineering. Vertical 4F2 diodes have been fabricated on an epitaxial Si stack consists of n+ / i / delta-doped p+ / i / n+ (NIPIN) layers by low temperature (sub-520°C) Si epitaxy. We experimentally demonstrate that while conventional NPN selectors exhibit severe sub-threshold slope degradation at high voltage, NIPIN selectors produce ideal subthreshold slope of ~120mV/decade with negligible degradation. Scaled devices show on-current density of 1-2MA/cm2 below 2V. High on-off current ratio of > 10 4 is estimated from experiments. The NIPIN shows significant improvements over NPN i.e. sub-2V operation (50% improvement) and non-linearity > 10 4 (i.e. 2 orders improvement). Perimeter scaling of current due to fringing fields is demonstrated experimentally which improves current density in area scaled devices. Further, the excellent device performance indicates the high quality Si epitaxy grown at sub-520°C that enables low trap density and high in situ dopant activation.

Low-resistance phosphorus-doped Si films through blue laser diode annealing

Abstract: The effect of activated annealing on Si films using a new semiconductor blue laser was studied for application to the thin-film transistor (TFT) system on a panel. As a result of the blue laser diode annealing of the continuous-wave (CW) scanning mode at 500 mm/s for 50-nm-thick heavily phosphorus-doped Si films, drastic crystallization occurred while maintaining the surface's smoothness. By irradiating the laser power between 5 and 8 W for chemical vapour deposition films, the grain size was successively controlled by forming micrograins to large grains as well as to anisotropic long crystal grains. Correspondingly, the resistivity decreased depending on the increase in the electron mobility while the high carrier concentration values were retained for the various grained structures. The dopant activation rate was estimated to be 100% in the Si network in spite of the polycrystalline phase. The heavily doped Si film is expected to be applied to electrodes in high-performance TFTs as an advanced low-tempe...

Highly-conductive B-doped nc-Si:H thin films deposited at room temperature by using SLAN ECR-PECVD

Abstract: Highly-conductive B-doped nc-Si:H was deposited at room temperature by using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD) with a slot antenna (SLAN ECR-PECVD) for low-temperature-process solar-cell and thin-film-transistor (TFT) applications. A novel SLAN ECR plasma source has a higher ionization rate compared to a RF plasma source, with a plasma density of ~1011 cm−3 at 1 mTorr. Spectroscopic ellipsometry, I–V, Raman spectroscopy, and UV-Vis spectroscopy measurements were used for the characterization. B-doped a-Si:H deposited at low H2 flow rates ( 30 sccm), it becomes highly conductive, 0.9–1.7 S/cm. The dopant activation energy is very low at 0.028 eV in spite of the room-temperature deposition. At 40 sccm of H2, the crystalline volume fraction of the film becomes 65%, and the crystal size is around 9.26 nm. Both the crystallinity and the crystal size increase with increasing flow of H2 and enable dopant activation. The optical bandgap varies from 2.07 to 2.35 eV with increasing H2 flow, and the film is useful as a wide-bandgap p-layer for use in p-i-n solar cells or for low-temperature-process TFT applications.

Millisecond Annealing for Semiconductor Device Applications

Abstract: Over the last decade millisecond annealing (MSA) has made the transition from a research tool to a key manufacturing technology for advanced complementary metal-oxide-semiconductor (CMOS) devices. MSA provides several unique process capabilities that have been very helpful for continued scaling of CMOS. One early application was for improving carrier activation in polysilicon gate electrodes, which reduces carrier depletion effects, providing increased gate capacitance. MSA also enables the formation of highly activated ultra-shallow junctions (USJ), which is essential for controlling short-channel effects while simultaneously minimizing the transistor’s parasitic resistance. New applications have emerged in silicide annealing, especially for NiSi contacts, where MSA can reduce the tendency for dopant deactivation, film agglomeration and for formation of “pipe defects”. As device scaling continues, the need to limit atomic diffusion and defect formation calls for ever-decreasing thermal budget, opening up new opportunities for MSA. Furthermore, the processing has to be compatible with new materials, including high-K dielectrics and metal gates, as well as the features needed for strain engineering and new channel materials. Millisecond annealing is usually performed through the use of pulsed high-power flash-lamps or scanned continuous wave laser beams. The paper describes the relative merits of these approaches, including flash-assisted RTP™ (fRTP™), where rapid wafer preheating is combined with pulsed surface heating to provide great flexibility in the design of thermal profiles. Such flexibility helps optimization in the trade-off between between dopant activation, diffusion, defect annealing and device integration requirements. Another important topic is process control, including issues of wafer temperature measurement and process uniformity. Finally the paper discusses emerging applications for millisecond annealing as a manufacturing technology for new types of semiconductor devices.

High performance sub-430°C epitaxial silicon PIN selector for 3D RRAM

Abstract: The high performance of Si based selection devices is constrained by the high processing temperature requirement (>700°C) for 3D storage memory application. Many high performance Si based selection devices have been demonstrated. Epitaxial [1] and poly PN junction diodes [2-3] have been demonstrated for unipolar RRAM while epitaxial NPN punch-through diodes [4] has been developed for bipolar RRAM as summarized in Table 1. However, Si based selection devices require high temperature (>700°C) epitaxy, CVD, or crystallization. The main challenges for low temperature process are (i) high dopant activation for on-current density (ii) low defects for low off-current. In this paper, we demonstrate that sub-430°C temperature Si diodes by Si MBE with excellent performance. 3D stacking by various strategies e.g. lateral epitaxial overgrowth on seed hole [5], is enabled by back-end compatible temperature of epitaxy.

Stimulated oxygen impurity gettering under ultra-shallow junction formation in silicon

Abstract: Ultra-shallow junctions were formed by low-energy As ion implantation followed by furnace annealing. It was found that a significant amount of oxygen is redistributed from the silicon bulk to the As-implanted region. Using a marker layer created by implantation of 18 O isotope, it is confirmed that a large number of interstitial oxygen atoms are transferred from the bulk of Si wafer to the surface during dopant activation annealing, which leads to an increase of the surface oxide thickness. Estimation of the oxygen diffusivity in silicon during the 950 ◦ C anneal, yields a value close to 1 × 10 −10 cm 2 s −1 which is more than an order of magnitude larger than the literature value which is close to 7 × 10 −12 cm 2 s −1 .

Impact of thermal history of Si nanowire fabrication process on Ni silicidation rate

Abstract: We have found that the thermal history of the fabrication process of Si nanowires (NWs) has a strong impact on the Ni silicidation rate. We compared the Ni silicidation rates in Si NWs fabricated by two different types of processes: the "Doping First" process, in which dopant activation annealing is completed before the lithography of NW structures, and the "Patterning First" process, in which NWs are firstly fabricated and then subjected to heat treatment entailing thermal oxidation and dopant activation. The Ni silicidation rate was appreciably higher in the Doping First process than in the Patterning First process. The difference is attributed to the residual stress rather than to the dopant concentration in Si-NWs. To control the silicidation rate in NWs, particular attention to the thermal history is necessary.

Laser spike annealing for n-type Ge junction & Ti silicide formation

Abstract: We investigate the use of sub-millisecond laser spike annealing (LSA) for two applications: n-type germanium shallow junction activation and titanium silicide formation. For Ge junction, impact of various process parameters including dwell times, peak annealing and substrate temperatures are evaluated. Arsenic dopant activation level of ~1e20 cm -3 is obtained. It is shown that short dwell time is preferred due to better junction scalability and reduced dopant loss. For Ti silicide, different analytical methods are used to identify the phases at various stages of LSA induced silicidation. Evidence of TiSi 2 C40 phase, which typically does not occur in conventional thermal annealing, is observed in LSA annealed samples.

Dopant profile engineering using ArF excimer laser, flash lamp and spike annealing for junction formation

Abstract: The aim of this study is to evaluate the feasibility to integrate excimer laser annealing (ELA) into the process flow to achieve higher doped and ideally box shaped profiles. The recrystallization, dopant distribution, and activation of boron or arsenic shallow implantations in germanium pre-amorphized silicon are investigated by comparing argon fluoride ELA, flash lamp annealing, and spike annealing. As a result the complete amorphous Silicon layer melts with ELA above 400 mJ/cm2 and subsequently recrystallizes taking the silicon substrate as crystal seed (ELA Liquid Phase Epitaxial Regrowth). The implanted dopants are uniformly distributed in the melted region. We achieved four to ten times sharper boron profiles and a dopant activation of up to 4×1020 cm−3 An active arsenic concentration of 1.6×1020 cm−3 was demonstrated.

Crystallization of Amorphous Silicon and Dopant Activation using Xenon Flash-Lamp Annealing (FLA)

Abstract: Flash-lamp annealing (FLA) has been investigated for the crystallization of a 60 nm amorphous silicon (a-Si) layer deposited by PECVD on display glass. Input factors to the FLA system included lamp intensity and pulse duration. Conditions required for crystallization included use of a 100 nm SiO2 capping layer, and substrate heating resulting in a surface temperature ∼ 460 °C. An irradiance threshold of ∼ 20 kW/cm2 was established, with successful crystallization achieved at a radiant exposure of 5 J/cm2, as verified using variable angle spectroscopic ellipsometry (VASE) and Raman spectroscopy. Nickel-enhanced crystallization (NEC) using FLA was also investigated, with results suggesting an increase in crystalline volume. Different combinations of furnace annealing and FLA were studied for crystallization and activation of samples implanted with boron and phosphorus. Boron activation demonstrated a favorable response to FLA, achieving a resistivity ρ < 0.01 Ω•cm. Phosphorus activation by FLA resulted in a resistivity ρ ∼ 0.03 Ω•cm.

Plasma Doping of InGaAs at Elevated Substrate Temperature for Reduced Sheet Resistance and Defect Formation

Abstract: Plasma doping (PLAD), a high-throughput ion implantation technique capable of achieving ultrashallow junctions and conformal doping of 3-D structures such as fin field-effect transistors, is investigated as an alternative to conventional beam-line ion implantation for InGaAs at advanced technology nodes. The PLAD at an elevated substrate temperature (ET-PLAD) is studied and reported for InGaAs for the first time. The ET-PLAD can give lower sheet resistance than room-temperature PLAD due to enhanced dopant incorporation. More crucially, an ET can help to prevent amorphization. After dopant activation anneal, residual corner defects are observed in small fins that are amorphized during plasma ion implantation, whereas fins that remain crystalline during plasma ion implantation are free of corner defects.

Deactivation of phosphorus in silicon due to implanted nitrogen

Abstract: Deactivation of phosphorus due to nitrogen incorporation was quantitatively investigated. Coimplantation was performed to produce nitrogen profiles overlapping phosphorus profiles in preamorphized silicon. Nitrogen was found to retard phosphorus activation after recrystallization of the amorphous layer. When phosphorus activation was completed, a gap of dopant activation level was observed between samples implanted with and without nitrogen. The gap of the activation level increased linearly with the doses of nitrogen and phosphorus. This implies formation of inactive complexes by pairing of phosphorus and nitrogen atoms. However, the gap disappeared when the peak profile of nitrogen shifted toward the surface during additional annealing at 750 °C for long times. This indicates that the complexes were not stable and therefore dissolved with nitrogen diffusion. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Effects of thermal annealing on the properties of N-implanted ZnS films

Abstract: N-ion-implantation to a fluence of 1 × 1015 ions/cm2 was performed on ZnS thin films deposited on glass substrates by using the vacuum evaporation method. The films were annealed in flowing nitrogen at 400 °C–500 °C after N-ion-implantation to repair the ion-beam-induced structural destruction and electrically activate the dopants. Effects of ion-implantation and post-thermal annealing on ZnS films were investigated by X-ray diffraction (XRD), photoluminescence (PL), optical transmittance, and electrical measurements. Results showed that the diffraction peaks and PL intensities were decreased by N-ion-implantation, but fully recovered by further annealing at 500 °C. In this experiment, all films exhibited high resistivity due to the partial dopant activation under 500 °C.

Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology

Abstract: We investigated using high dose (5E16/cm) Ge beam-line ion implantation in combination with laser melt annealing as an alternative to Ge-epi by CVD to form high quality single crystal Ge-epilayer by LPE (liquid phase epitaxy) that is very uniform, thin 10-25nm and localized for high mobility Ge-channels. The implant resulted in 7nm amorphous Ge deposition by a method called dose controlled deposition (DCD). A 515nm laser was used to vary the melt depth from 9nm to 500nm based on laser anneal pulse duration and power level. Ellipsometer was used to measure the surface amorphous layer thickness while therma-wave (TW) analysis was used to monitor Ge implant damage recovery after LPE. SIMS depth profiles showed Ge surface concentration varied from 100% down to 2% based on the laser melt depth. X-TEM analysis showed the transformation of deposited amorphous Ge surface layer to single crystal Ge after laser melt and LPE. Sb implantation at two dose levels of 3E15/cm and 3E13/cm was used to examine laser melt annealing effects on n-type dopant activation and electron mobility in Ge. Special Hx-probe tips on the 4PP system was required to measure sheet resistance and CAOT/DHE method was used for Differential Hall Effect measurements.

Implant dopant activation comparison between silicon and germanium

Abstract: We report room temperature p-type acceptor formation in Ge from B and C implant damage up to a level of 120Ω/□ or 1E19/cm3. For n-type dopant implants in Ge we found that an oxide surface capping layer was required above 625°C to prevent dopant surface loss. P followed by As then Sb gave the best dopant activation and at the same low temperature anneal B, P, As and Sb Rs values were always lower in Ge by 1.3x to 3x than in Si possibly directly related to the higher mobility ratio in Ge to Si and differences in Ge dopant surface loss and segregation into oxide.

Engineering of p-n junction for high efficiency semiconducting BaSi2 based thin film solar cells

Abstract: Fabrication of p-n structure for any photovoltaic device is a crucial step. In this paper optimized growth of B-doped p-BaSi2 layer grown by molecular beam epitaxy on Si(111) were presented first. The acceptor level of the B-atoms was estimated to be approximately 23 meV. High hole concentrations exceeding 1×1020 cm-3 were achieved via dopant activation using RTA at 800 °C in Ar. By using this optimized growth condition a novel p-n structure were also grown on un-doped BaSi2 and Si(111) substrate. SIMS profile gives us no diffusion and segregation tendency across the homojunction as well as across the hetrojunction of Solar cells. The novel p-n junction is one step behind the practical semiconducting BaSi2 solar cells p-n junction.

Lateral energy band engineering of Al 2 O 3 /III-nitride interfaces

Abstract: In this work, we have used electrostatic engineering of the ALD dielectric/III-nitride interface to do lateral band engineering in a III-nitride HEMT. Due to challenges related to dopant activation and damage anneal, traditional ion implantation and diffusion techniques for lateral band engineering that are commonly used in other semiconductors, cannot be applied easily in the III-nitride system. We have developed an alternate method that uses surface fixed charges to engineer lateral energy band profiles, and used this to demonstrate an enhancement-mode AlGaN/GaN HEMT without any gate recess. Metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) based on the III-Nitride system can efficiently suppress gate leakage enabling lower gate-channel spacing for high frequency transistors, and low off-state leakage for power switching devices. Conventional normally-off MISHEMTs require precise etching control for recess gate [1] or heavy p+ doping for the junction gate [2]. However, plasma etching may induce variation of electrical characteristics caused by surface damage while p-doping can cause hysteresis. In this work, we show a new technique to achieve normally off AlGaN/GaN transistors. Our method exploits the interface properties of dielectric/III-nitride, where a high density of fixed charges of the order of 1 μC/cm 2 can be formed the interface of atomic layer deposited (ALD) dielectrics on GaN and AlN[3-5]. In this work, we use the combination of oxygen plasma and post metallization anneal (PMA) treatments to engineer the Al 2 O 3 /AlGaN (AlN) interface fixed charges. Based on this technology, lateral energy band engineering by patterning ALD Al 2 O 3 is demonstrated. This technology provides a new approach to recess-free and doping-free normally-off MOSFETs /MISHEMTs.