Showing papers on "Gate oxide published in 2006"

High dielectric constant gate oxides for metal oxide Si transistors

Abstract: The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

Field-effect transistor including transparent oxide and light-shielding member, and display utilizing the transistor

Abstract: A field-effect transistor includes a substrate, a source electrode, a drain electrode, a gate electrode, a gate-insulating film, and an active layer. The active layer contains an oxide having a transmittance of 70% or more in the wavelength range of 400 to 800 nm. A light-shielding member is provided as a light-shielding structure for the active layer, for example, on the bottom face of the substrate.

Low voltage flexible organic/transparent transistor for selective gas sensing, photodetecting and CMOS device applications

Abstract: A thin film transistor (TFT) includes a source electrode, a drain electrode, and a gate electrode. A gate insulator is coupled to the source electrode, drain electrode, and gate electrode. The gate insulator includes room temperature deposited high-K materials so as to allow said thin film transistor to operate at low operating voltage.

High-performance ZnO thin-film transistors on gate dielectrics grown by atomic layer deposition

Abstract: We fabricated high-performance ZnO thin-film transistors on gate dielectrics of HfO2, HfSiOx, and Al2O3, grown by atomic layer deposition (ALD). Devices on HfO2 had a mobility of 12.2cm2∕Vs with a threshold voltage of 2.6V and subthreshold slope of 0.5V∕decade. Device performance on Al2O3 depended on synthesis temperature. For 100nm thick Al2O3, synthesized at 200°C, ZnO devices had a mobility of 17.6cm2∕Vs with a threshold voltage of 6V and less than ∼0.1nA gate leakage at 20V. The overall trends were that devices on Hf oxides had a lower threshold voltage, while the gate leakage current density was lower on Al2O3. Device characteristics for all ALD dielectrics exhibited negligibly small hysteresis, suggesting a low defect density at the interface of ZnO with the gate dielectric.

Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors

Abstract: As the characteristics of insulted gate transistors [like metal–oxide–semiconductor field-effect transistors and insulated gate bipolar transistors (IGBTs)] have been constantly improving, their utilization in power converters operating at higher and higher frequencies has become more common. However, this, in turn, leads to fast current and voltage transitions that generate large amounts of electromagnetic interferences over wide frequency ranges. In this paper, a new active gate voltage control (AGVC) method is presented. It allows us to control the values of at turn-on and at turn-off for insulated gate power transistors, by acting directly on the input gate voltage shape. In an elementary switching cell, it enables us to strongly reduce over-current generated by the reverse recovery of the free-wheeling diode at turn-on, and oscillations of the output voltage across the transistor at turn-off. In the following sections, the AGVC in open and closed-loop for IGBT is presented, and its performance is compared with that of a more conventional method, i.e., increasing the gate resistance. Robustness of the AGVC is estimated under variations of dc-voltage supply and transistor switched current.

Semiconductor memory device and method of fabricating the same

Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained; pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

Ald of silicon films on germanium

Abstract: The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a tantalum nitride gate electrode on a hafnium dioxide gate dielectric on the silicon film (TaN/HfO2/Si/Ge), which produces a reliable high dielectric constant (high k) electronic structure having higher charge carrier mobility as compared to silicon substrates. This structure may be useful in high performance electronic devices. The structure is formed by ALD deposition of a thin silicon layer on a germanium substrate surface, and then ALD forming a hafnium oxide gate dielectric layer, and a tantalum nitride gate electrode. Such a structure may be used as the gate of a MOSFET, or as a capacitor. The properties of the dielectric may be varied by replacing the hafnium oxide with another gate dielectric such as zirconium oxide (ZrO2), or titanium oxide (TiO2).

Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer

Abstract: We demonstrate the electrical properties of metal-oxide-semiconductor capacitors on molecular beam epitaxial GaAs in situ passivated with ultrathin amorphous Si (a-Si) layer and with ex situ deposited HfO2 gate oxide and TaN metal gate. Minimum thickness of the Si interface passivation layer of 1.5 nm is needed to prevent the Fermi level pinning and provide good capacitance-voltage characteristics with equivalent oxide thickness of 2.1 nm and leakage current of ⩽1.0mA∕cm2. Transmission electron microscopy analysis showed that the Si layer was oxidized up to 1.4 nm during ex situ processing while the interface between the GaAs and a-Si remained atomically sharp without any sign of interfacial reaction.

Method of manufacturing flash memory device

Abstract: A method for manufacturing a flash memory device including the steps of forming a gate oxide film for high voltage on the whole surface of a semiconductor substrate on which a cell region, a low voltage region and a high voltage region have been formed, etching the gate oxide film for high voltage formed in the cell region and the low voltage region by a predetermined depth, by forming photoresist patterns to expose the gate oxide film for high voltage formed in the cell region and the low voltage region, and performing a wet etching process using the photoresist patterns as an etching mask, removing the entire gate oxide film for high voltage formed in the cell region and the low voltage region, by performing a cleaning process on the resulting structure, removing the photoresist patterns, forming a floating gate electrode and a control gate electrode, by sequentially forming a tunnel oxide film, a first polysilicon film, a second polysilicon film, a dielectric film, a third polysilicon film and a metal silicide film on the whole surface of the resulting structure, and patterning the resulting structure, and forming source and drain regions, by implanting ions by using the gate electrodes as an ion implant mask.

Investigations of HfO2∕AlGaN∕GaN metal-oxide-semiconductor high electron mobility transistors

Abstract: We report the studies of AlGaN∕GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) using reactive-sputtered HfO2 as the gate dielectric and the surface passivation layer. X-ray photoemission method reveals a conduction-band offset of 1.71eV for the HfO2∕GaN heterostructure. The dielectric constant of HfO2 is estimated to be 21 by capacitance-voltage measurements. MOS-HEMTs with a 1.5-μm-long gate exhibit a maximum drain current of 830mA∕mm and a peak transconductance of 115mS∕mm, while the gate leakage current is at least five orders of magnitude lower than that of the reference HEMTs. Good surface passivation effects of HfO2 have also been confirmed by pulsed gate measurements, with MOS-HEMTs showing a significant drain current recovery from current collapse observed in HEMTs.

Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors

Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Methods and devices for improved charge management for three-dimensional and color sensing

Abstract: TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X- dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably a potential barrier is implanted between adjacent gates and a bias gate is formed intermediate a gate and associated source region. Resultant detector structures can be operated at the more extreme gate voltages that are desirable for high performance.

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

Abstract: As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.

Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric

Abstract: Atomic layer deposition (ALD) Al2O3 is a high-quality gate dielectric on III-V compound semiconductor with low defect density, low gate leakage, and high thermal stability. The high-quality of Al2O3∕InGaAs interface surviving from high temperature annealing is verified by excellent capacitance-voltage (CV) curves showing sharp transition from depletion to accumulation with “zero” hysteresis, 1% frequency dispersion per decade at accumulation capacitance, and strong inversion at split CV measurement. An enhancement-mode n-channel InGaAs metal-oxide-semiconductor field-effect-transistor is also demonstrated by forming true inversion channel at Al2O3∕InGaAs interface.

Bio-organic-semiconductor-field-effect-transistor based on deoxyribonucleic acid gate dielectric

Abstract: Organic-based field-effect transistors (OFETs) utilize organic semiconductor materials with low electron mobilities and organic gate oxide materials with low dielectric constants. These have rendered devices with slow operating speeds and high operating voltages, compared with their inorganic silicon-based counter parts. Using a deoxyribonucleic acid (DNA)-based biopolymer, derived from salmon milt and roe sac waste by-products, for the gate dielectric region, we have fabricated an OFET device that exhibits very promising current-voltage characteristics compared with using other organic-based dielectrics. With minimal optimization, using a thin film of DNA-based biopolymer as the gate insulator and pentacene as the semiconductor, we have demonstrated a bio-organic-FET, or BiOFET, in which the current was modulated over three orders of magnitude using gate voltages less than 10V.

Semiconductor device having oxide semiconductor layer and manufacturing method thereof

Abstract: The invention provides an active matrix liquid crystal display device comprising a gate electrode over a substrate; an insulating film over the gate electrode; an oxide semiconductor film over the gate electrode with the insulating film interposed there between; a channel protective film formed over the oxide semiconductor film; a source electrode and a drain electrode formed over the oxide semiconductor film and the channel protective film; a passivation film comprising an insulating material formed over at least the source electrode, the drain electrode, the channel protective film and the oxide semiconductor film; and a pixel electrode formed over the passivation film and electrically connected to one of the source electrode and the drain electrode.

Advanced cmos using super steep retrograde wells

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer ( 110 ) beneath the gate dielectric ( 50 ) and source and drain regions ( 80 ) of a MOS transistor. The carbon containing layer ( 110 ) will prevent the diffusion of dopants into the region ( 40 ) directly beneath the gate dielectric layer ( 50 ).

Field-effect transistor

Abstract: A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.

Semiconductor device including FinFET having metal gate electrode and fabricating method thereof

Abstract: Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

Flash memory cell and methods for programming and erasing

Abstract: Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

Trench-gate field effect transistors and methods of forming the same

Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

Enhancement-Mode $hboxSi_3hboxN_4hbox/AlGaN/GaN$ MISHFETs

Abstract: Enhancement-mode Si3N4/AlGaN/GaN metal-insulator-semiconductor HFETs (MISHFETs) with a 1-mum gate footprint are demonstrated by combining CF4 plasma treatment technique and a two-step Si3N4 deposition process. The threshold voltage has been shifted from -4 [for depletion-mode HFET] to 2 V using the techniques. A 15-nm Si3N4 layer is inserted under the metal gate to provide additional isolation between the gate Schottky contact and AlGaN surface, which can lead to reduced gate leakage current and higher gate turn-on voltage. The two-step Si 3N4 deposition process is developed to reduce the gate coupling capacitances in the source and drain access region, while assuring the plasma-treated gate region being fully covered by the gate electrode. The forward turn-on gate bias of the MISHFETs is as large as 7 V, at which a maximum current density of 420 mA/mm is obtained. The small-signal RF measurements show that the current gain cutoff frequency (fT) and power gain cutoff frequency (fmax) are 13.3 and 23.3 GHz, respectively

Electrolyte-gated charge accumulation in organic single crystals

Abstract: Comparative studies of electrolyte-gated and SiO2-gated field-effect transistors have been carried out on rubrene single crystals by experimentally estimating their accumulated charges. The capacitance of the electrolyte gate at 1mHz was 15μF∕cm2, which is more than two orders of magnitude larger than that of the 100-nm-thick SiO2 gate dielectric. The maximum carrier density in the electrolyte gate was 0.33hole∕molecule, which is considerably larger than that in the SiO2 gate. Furthermore, the transfer characteristics of the electrolyte-gate field-effect transistor showed reversible-peak behavior at an accumulated carrier density of 0.23hole∕molecule.

Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers

Abstract: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide A control gate opposes the floating gate The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator And, the control gate includes a polysilicon control gate having a metal layer, having a different work function from the metal layer formed on the floating gate, formed thereon in contact with the low tunnel barrier intergate insulator

Enabling gate dielectric design for all solution-processed, high-performance, flexible organic thin-film transistors.

Abstract: A novel solution-processed, compositionally and structurally stable dual-layer gate dielectric composed of a UV-cured poly(4-vinyl phenol)-co-poly(methyl methacrylate) bottom layer and a thermally cross-linked poly(methyl silsesquioxane) top layer for organic thin-film transistors is described. This gate dielectric design, coupled with compatible solution-processable semiconductor and conductor materials, has enabled fabrication of all solution-processed, high-performance organic thin-film transistors on flexible substrates. High field-effect mobility and current on/off ratio, together with other desirable transistor properties, are demonstrated.

Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Switch mode power amplifier using fet with field plate extension

Abstract: Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.

Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same

Abstract: A semiconductor memory device includes: a semiconductor substrate, on which an impurity diffusion layer is formed in a cell array area; a gate wiring stack body formed on the cell array area, in which multiple gate wirings are stacked and separated from each other with insulating films; a gate insulating film formed on the side surface of the gate wiring stack body, in which an insulating charge storage layer is contained, pillar-shaped semiconductor layers arranged along the gate wiring stack body, one side surfaces of which are opposed to the gate wiring stack body via the gate insulating film, each pillar-shaped semiconductor layer having the same conductivity type as the impurity diffusion layer; and data lines formed to be in contact with the upper surfaces of the pillar-shaped semiconductor layers and intersect the gate wirings.

Semiconductor device and method of manufacturing the same

Abstract: A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.