Showing papers on "Gate oxide published in 2010"

Germanium FinFETs with Metal Gates and Stressors

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide

Abstract: We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO2/4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl3). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm2/V · s by POCl3 annealing at 1000°C.

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.

Self-aligned contacts

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations

Strained channel integrated circuit devices

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Vertical-type non-volatile memory devices and methods of manufacturing the same

Abstract: In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

Structure and method for replacement gate mosfet with self-aligned contact using sacrificial mandrel dielectric

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Evolution of structural defects associated with electrical degradation in AlGaN/GaN high electron mobility transistors

Abstract: We have investigated the surface morphology of electrically stressed AlGaN/GaN high electron mobility transistors using atomic force microscopy and scanning electron microscopy after removing the gate metallization by chemical etching. Changes in surface morphology were correlated with degradation in electrical characteristics. Linear grooves formed along the gate edges in the GaN cap layer for all electrically stressed devices. Beyond a critical voltage that corresponds to a sharp increase in the gate leakage current, pits formed on the surface at the gate edges. The density and size of the pits increase with stress voltage and time and correlate with degradation in the drain current and current collapse. We believe that high mechanical stress in the AlGaN layer due to high-voltage stressing is relieved by the formation of these defects which act as paths for gate leakage current and result in electron trapping and degradation in the transport properties of the channel underneath.

Three-terminal field effect devices utilizing thin film vanadium oxide as the channel layer

Abstract: Electrostatic control of the metal-insulator transition (MIT) in an oxide semiconductor could potentially impact the emerging field of oxide electronics. Vanadium dioxide (VO2) is of particular interest due to the fact that the MIT happens in the vicinity of room temperature and it is considered to exhibit the Mott transition. We present a detailed account of our experimental investigation into three-terminal field effect transistor-like devices using thin film VO2 as the channel layer. The gate is separated from the channel through an insulating gate oxide layer, enabling true probing of the field effect with minimal or no interference from large leakage currents flowing directly from the electrode. The influence of the fabrication of multiple components of the device, including the gate oxide deposition, on the VO2 film characteristics is discussed. Further, we discuss the effect of the gate voltage on the device response, point out some of the unusual characteristics including temporal dependence. A re...

A 0.13 $\mu{\hbox {m}}$ SiGe BiCMOS Technology Featuring f $_{T} $ /f $_{\max}$ of 240/330 GHz and Gate Delays Below 3 ps

Abstract: A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies fT of 240 GHz, maximum oscillation frequencies fmax of 330 GHz, and breakdown voltages BVCEO of 1.7 V along with high-voltage HBTs (fT = 50 GHz,fmax = 130 GHz, BVCEO = 3.7 V) integrated in a dual gate oxide RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators with fundamental-mode oscillation frequencies above 200 GHz are demonstrated.

Transistor and display device

Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Growth and Performance of Yttrium Oxide as an Ideal High-κ Gate Dielectric for Carbon-Based Electronics

Abstract: High-quality yttrium oxide (Y2O3) is investigated as an ideal high-κ gate dielectric for carbon-based electronics through a simple and cheap process. Utilizing the excellent wetting behavior of yttrium on sp2 carbon framework, ultrathin (about few nm) and uniform Y2O3 layers have been directly grown on the surfaces of carbon nanotube (CNT) and graphene without using noncovalent functionalization layers or introducing large structural distortion and damage. A top-gate CNT field-effect transistor (FET) adopting 5 nm Y2O3 layer as its top-gate dielectric shows excellent device characteristics, including an ideal subthreshold swing of 60 mV/decade (up to the theoretical limit of an ideal FET at room temperature). The high electrical quality Y2O3 dielectric layer has also been integrated into a graphene FET as its top-gate dielectric with a capacitance of up to 1200 nF/cm2, showing an improvement on the gate efficiency and on state transconductance of over 100 times when compared with that of its back-gate cou...

Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing

Abstract: An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

Air Stable Cross-Linked Cytop Ultrathin Gate Dielectric for High Yield Low-Voltage Top-Gate Organic Field-Effect Transistors

Abstract: We demonstrate the use of a cross-linking chemistry for an amorphous fluoropolymer gate dielectric, poly(perfluorobutenylvinylether) commercially known as Cytop. Spin-coated films of Cytop exhibit good gate insulating properties as well as provide excellent OFET operational stability. However, these devices operate at large voltages because the dielectric layer thickness is typically ∼450−600 nm. When the thickness of a Cytop dielectric layer is decreased below 200 nm, the device yields are dramatically reduced due to pinhole formation. Our new cross-linked Cytop (C-Cytop) formulation deposited by spin-coating enables uniform thin films on top of various organic semiconductors that exhibits low gate leakage current densities ( 2 MV cm−1). Our approach results in C-Cytop dielectric films as thin as 50 nm, thus allowing the fabrication of reliable p- and n-channel top-gate OFETs operating at very low-voltages (<5 V). The most remarkable properties of thi...

Semiconductor device and semiconductor integrated circuit using the same

Abstract: The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

Methods of fabricating silicon oxide layers using inorganic silicon precursors and methods of fabricating semiconductor devices including the same

Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure. The first and third dielectric layers formed of the silicon oxide are formed using a first gas including an inorganic silicon precursor, a second gas including hydrogen gas or a hydrogen component, and a third gas including an oxide gas.

Poly-si thin film transistor and organic light-emitting display having the same

Abstract: A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.

Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric

Abstract: An improved double-gate tunnel field-effect transistor structure with superior performance is proposed. The originality consists in the introduction of a low-k spacer that is combined with a high-k gate dielectric. Numerical simulations demonstrate that the use of the low-k spacer and high-k gate dielectric leads to a high on-current, ION, and reduced subthreshold slope. The proposed structure increases ION by a factor of 3.8 and reduces the subthreshold slope by a factor of 2 compared to other structures described in literature.

World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS

Abstract: World's first monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor I on /I off ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation.

Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices—Application to NBTI

Abstract: The statistical distribution of negative bias temperature instability (NBTI) in deca-nanometer p-channel FETs is discussed. An exponential distribution of threshold voltage shifts due to a single charge trapped in the gate oxide is observed, resulting in single-charge shifts exceeding 30 mV in some of the studied 35-nm-long and 90-nm-wide devices. The exponential distribution is justified with a simple channel percolation model. Combined with the assumption of the Poisson-distributed number of trapped gate oxide charges, an analytical description of the total NBTI threshold voltage shift distribution is derived. This allows, among other things, linking its first two moments with the average number of defects per device, which is found < 10 in the studied devices.

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

Abstract: In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

The impact of gate dielectric materials on the light-induced bias instability in Hf–In–Zn–O thin film transistor

Abstract: This study examined the effect of gate dielectric materials on the light-induced bias instability of Hf–In–Zn–O (HIZO) transistor The HfOx and SiNx gated devices suffered from a huge negative threshold voltage (Vth) shift (>11 V) during the application of negative-bias-thermal illumination stress for 3 h In contrast, the HIZO transistor exhibited much better stability (<20 V) in terms of Vth movement under identical stress conditions Based on the experimental results, we propose a plausible degradation model for the trapping of the photocreated hole carrier either at the channel/gate dielectric or dielectric bulk layer

Carbon Nanotubes for VLSI: Interconnect and Transistor Applications

Abstract: Carbon nanotubes (CNTs) offer unique properties such as the highest current density, ballistic transport, ultrahigh thermal conductivity, and extremely high mechanical strength. Because of these remarkable properties, they have been expected for use as wiring materials and as alternate channel materials for extending complementary metal-oxide-semiconductor (CMOS) performance in future very large scale integration (VLSI) technologies. In this paper, we report the present status of CNT growth technologies and the applications for via interconnects (vertical wiring) and field-effect transistors (FETs). We fabricated CNT via and evaluated its robustness over a high-density current. In our technology, multiwalled carbon nanotubes (MWNTs) were successfully grown at temperatures as low as 365°C using Co catalyst nanoparticles, which were formed and deposited by a custom-designed particle generation and deposition system. The density of MWNTs grown at 450°C reaches more than 1×1012/cm2. MWNTs were grown in via holes with a diameter as small as 40 nm. The resistance of CNT vias with a diameter of 160 nm was found to be of the same order as that of tungsten plugs. The CNT via was able to sustain a current density as high as 5.0×106A/cm2 at 105°C for 100 h without any deterioration in its properties. We propose a Si-process compatible technique to control carrier polarity of CNFETs by utilizing fixed charges introduced by the gate oxide. High-performance p- and n-type CNFETs and CMOS inverters with stability in air have been realized.

All-amorphous-oxide transparent, flexible thin-film transistors. Efficacy of bilayer gate dielectrics.

Abstract: Optically transparent and mechanically flexible thin-film transistors (TF-TFTs) composed exclusively of amorphous metal oxide films are fabricated on plastic substrates by combining an amorphous Ta2O5/SiOx bilayer transparent oxide insulator (TOI) gate dielectric with an amorphous zinc−indium−tin oxide (a-ZITO) transparent oxide semiconductor (TOS) channel and a-ZITO transparent oxide conductor (TOC) electrodes The bilayer gate dielectric is fabricated by the post-cross-linking of vapor-deposited hexachlorodisiloxane-derived films to form thin SiOx layers (v-SiOx) on amorphous Ta2O5 (a-Ta2O5) films grown by ion-assisted deposition at room temperature The a-Ta2O5/v-SiOx bilayer TOI dielectric integrates the large capacitance of the high dielectric constant a-Ta2O5 layer with the excellent dielectric/semiconductor interfacial compatibility of the v-SiOx layer in a-ZITO TOS-based TF-TFTs These all-amorphous-oxide TF-TFTs, having a channel length and width of 100 and 2000 μm, respectively, perform far bett

Revealing Buried Interfaces to Understand the Origins of Threshold Voltage Shifts in Organic Field-Effect Transistors

Abstract: The semiconductor of an organic field-effect transistor is stripped with adhesive tape, yielding an exposed gate dielectric, accessible for various characterization techniques. By using scanning Kelvin probe microscopy we reveal that trapped charges after gate bias stress are located at the gate dielectric and not in the semiconductor. Charging of the gate dielectric is confirmed by the fact that the threshold voltage shift remains, when a pristine organic semiconductor is deposited on the exposed gate dielectric of a stressed and delaminated field-effect transistor.

Accumulation type FinFET, circuits and fabrication method thereof

Abstract: A FinFET includes a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have the first type dopant. The channel includes a Ge, SiGe, or III-V semiconductor. A gate dielectric layer is located over the channel and a gate is located over the gate dielectric layer.

Method and apparatus for enhancing channel strain

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer.

Thin film transistor array panel and method for manufacturing the same

Abstract: A TFT array panel including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain electrode, and a pixel electrode connected to the drain electrode is provided. The TFT array panel further includes a protection layer including Si under at least one of the gate insulating layer and the passivation layer to enhance reliability.

High-Performance Integrated Dual-Gate AlGaN/GaN Enhancement-Mode Transistor

Abstract: In this letter, we present a new AlGaN/GaN enhancement-mode (E-mode) transistor based on a dual-gate structure. The dual gate allows the transistor to combine an E-mode behavior with low on-resistance and very high breakdown voltage. The device utilizes an integrated gate structure with a short gate controlling the threshold voltage and a long gate supporting the high-voltage drop from the drain. Using this new dual-gate technology, AlGaN/GaN E-mode transistors grown on a Si substrate have demonstrated a high threshold voltage of 2.9 V with a maximum drain current of 434 mA/mm and a specific on-resistance of 4.3 m Ω·cm2 at a breakdown voltage of 643 V.

FinFET-compatible metal-insulator-metal capacitor

Abstract: At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.