Showing papers on "Subthreshold conduction published in 2003"

High performance fully-depleted tri-gate CMOS transistors

Abstract: Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

Carbon Nanotube Field-Effect Transistors With Integrated Ohmic Contacts and High-k Gate Dielectrics

Abstract: High performance enhancement mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal-tube contacts, high dielectric constant HfO2 films as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes. The combination of these elements affords high ON currents, subthreshold swings of ~ 70-80 mV/decade, and allows for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles that of MOSFETs and can impart excellent OFF states to nanotube FETs under aggressive vertical scaling. This presents an important advantage over devices with metal source/drain, or devices commonly referred to as Schottky barrier FETs.

From subthreshold to firing-rate resonance.

Abstract: First published December 27, 2002; 10.1152/jn.00955.2002. Many types of neurons exhibit subthreshold resonance. However, little is known about whether this frequency preference influences spike emi...

A low-voltage low-power voltage reference based on subthreshold MOSFETs

Abstract: In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.

HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects

Abstract: This report introduces HotLeakage, an architectural model for subthreshold and gate leakage that we have developed here at the University of Virginia. The most important features of HotLeakage are the explicit inclusion of temperature, voltage, gate leakage, and parameter variations, and the ability to recalculate leakage currents dynamically as temperature and voltage change due to operating conditions, DVS techniques, etc. HotLeakage provides default settings for 180nm through 70nm technologies for modeling cache and register files, and provides a simple interface for selecting alternate parameter values and for modeling alternative microarchitecture structures. It also provides models for several extant cache leakage control techniques, with an interface for adding further techniques. HotLeakage is currently a semi-independent module for use with SimpleScalar, but is sufficiently modular that it should be fairly easy to port to other simulators. Because sub-threshold leakage currents are exponentially dependent on temperature and voltage, because gate leakage is growing so rapidly, and because parameter variations can have a profound effect on simulation accuracy, we hope that HotLeakage will serve as a useful tool for microarchitects to more accurately evaluate issues related leakage power. HotLeakage is available for download athttp://lava.cs.virginia.edu/HotLeakage

Theta oscillation coupled spike latencies yield computational vigour in a mammalian sensory system

Abstract: Theoretical work carried out almost a decade ago proposed that subthreshold oscillations in membrane potential could be used to convert synaptic current strength into a code reliant on action potential (AP) latencies. Using whole-cell recordings we present experimental evidence for the occurrence of prominent network-driven subthreshold theta oscillations in mitral cells of the mouse olfactory bulb. Activity induced by both injected current and sensory input was accurately reflected in initial AP latency from the beginning of each oscillation cycle. In a network model we found that an AP latency code rather than AP number or instantaneous firing rate provided computational speed and high resolution, and was easily implemented. This coding strategy was also found to be invariant to the total input current as long as the relative input intensities to glomeruli remained constant. However, it was highly sensitive to changes in the ratios of the input currents and improved by lateral inhibitory mechanisms. Since the AP latency-based coding scheme was dependent on the subthreshold oscillation we conclude that the theta rhythm serves a functional role in temporally reformatting the strengths and patterns of synaptic input in this sensory system.

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Abstract: Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

Design and optimization of multithreshold CMOS (MTCMOS) circuits

Abstract: Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuit's routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.

Active-matrix display device and method of driving the same

Abstract: In an active-matrix display device and a method for driving the active-matrix display device, a fifth transistor is connected between a power line and a drain terminal of a first transistor so that a power-supply voltage, namely the fixed voltage required for the compensation of the threshold voltage, is supplied by the power line via a fifth transistor and not by a signal line Thus, a sufficient length of time for the threshold voltage compensation period can be maintained, and a second transistor of each pixel can accurately be compensated for threshold voltage irregularities

Review and future prospects of low-voltage RAM circuits

Abstract: This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, VT, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

Electro-optical device and semiconductor circuit

Abstract: A high performance circuit is formed by using a TFT with less fluctuation in characteristics, and a semiconductor device including such a circuit is formed. When the TFT is formed, first, a base film and a semiconductor film are continuously formed on a quartz substrate without exposing to the air. After the semiconductor film is crystallized by using a catalytic element, the catalytic element is removed. In the TFT formed in such a process, fluctuation in electrical characteristics such as a threshold voltage and a subthreshold coefficient is extremely small. Thus, it is possible to form a circuit, such as a differential amplifier circuit, which is apt to receive an influence of characteristic fluctuation of a TFT.

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems

Abstract: While dynamic power consumption has traditionally been the primary source of power consumption, leakage power is becoming an increasingly important concern as technology feature size continues to shrink. Previous system-level approaches focus on reducing power consumption without considering leakage power consumption. To overcome this limitation, we propose a two-phase approach to combine dynamic voltage scaling (DVS) and adaptive body biasing (ABB) for distributed real-time embedded systems. DVS is a powerful technique for reducing dynamic power consumption quadratically. However, DVS often requires a reduction in the threshold voltage that increases subthreshold leakage current exponentially and, hence, subthreshold leakage power consumption. ABB, which exploits the exponential dependence of subthreshold leakage power on the threshold voltage, is effective in managing leakage power consumption. We first derive an energy consumption model to determine the optimal supply voltage and body bias voltage under a given clock frequency. Then, we analyze the tradeoff between energy consumption and clock period to allocate slack to a set of tasks with precedence relationships and real-time constraints. Based on this two-phase approach, we propose a new system-level scheduling algorithm that can optimize both dynamic power and leakage power consumption by performing DVS and ABB simultaneously for distributed real-time embedded systems. Experimental results show that the average power reduction of our technique with respect to DVS alone is 37.4% for the 70-nm technology.

Gate leakage reduction for scaled devices using transistor stacking

Abstract: In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.

Ultra-low-power DLMS adaptive filter for hearing aid applications

Abstract: We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Abstract: Dramatic increase of subthreshold, gate and reverse biased junction band-to-band tunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2-D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a sum of current sources (SCS). The SCS transistors model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.

Analysis and minimization techniques for total leakage considering gate oxide leakage

Abstract: In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin recording as a means to reduce I/sub gate/ due to the dependencies of gate leakage on stack node voltages.

Improved independent gate N-type FinFET fabrication and characterization

Abstract: N-type independent gate FinFETs (IGFinFETs) have been fabricated and characterized. Previous published results for this structure highlighted processing deficiencies. Several process enhancements have improved device results beyond those previously reported. These process improvements are presented, and the resulting device is demonstrated. Device results for 2 micron channel length devices are shown. Six decades of drain current suppression and low gate leakage currents are achieved. Subthreshold slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V are demonstrated. This device combines the behavioral characteristics of independent-double-gate MOSFETs with the processing advantages and integration of FinFETs.

Modeling and estimation of total leakage current in nano-scaled-CMOS devices considering the effect of parameter variation

Abstract: In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50 nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.

Firing-rate resonance in a generalized integrate-and-fire neuron with subthreshold resonance

Abstract: Neurons that exhibit a peak at finite frequency in their membrane potential response to oscillatory inputs are widespread in the nervous system. However, the influence of this subthreshold resonance on spiking properties has not yet been thoroughly analyzed. To this end, generalized integrate-and-fire models are introduced that reproduce at the linear level the subthreshold behavior of any given conductance-based model. A detailed analysis is presented of the simplest resonant model of this kind that has two variables: the membrane potential and a supplementary voltage-gated resonant variable. The firing-rate modulation created by a noisy weak oscillatory drive, mimicking an in vivo environment, is computed numerically and analytically when the dynamics of the resonant variable is slow compared to that of the membrane potential. The results show that the firing-rate modulation is shaped by the subthreshold resonance. For weak noise, the firing-rate modulation has a minimum near the preferred subthreshold frequency. For higher noise, such as that prevailing in vivo, the firing-rate modulation peaks near the preferred subthreshold frequency.

Characterization of subthreshold voltage fluctuations in neuronal membranes

Abstract: Synaptic noise due to intense network activity can have a significant impact on the electrophysiological properties of individual neurons. This is the case for the cerebral cortex, where ongoing activity leads to strong barrages of synaptic inputs, which act as the main source of synaptic noise affecting on neuronal dynamics. Here, we characterize the subthreshold behavior of neuronal models in which synaptic noise is represented by either additive or multiplicative noise, described by Ornstein-Uhlenbeck processes. We derive and solve the Fokker-Planck equation for this system, which describes the time evolution of the probability density function for the membrane potential. We obtain an analytic expression for the membrane potential distribution at steady state and compare this expression with the subthreshold activity obtained in Hodgkin-Huxley-type models with stochastic synaptic inputs. The differences between multiplicative and additive noise models suggest that multiplicative noise is adequate to describe the high-conductance states similar to in vivo conditions. Because the steady-state membrane potential distribution is easily obtained experimentally, this approach provides a possible method to estimate the mean and variance of synaptic conductances in real neurons.

Exact analytical solution of channel surface potential as an explicit function of gate voltage in undoped-body MOSFETs using the Lambert W function and a threshold voltage definition therefrom

Abstract: Two useful applications of the Lambert W function to undoped-body MOSFET modeling are presented. Firstly, it is applied to the problem of inverting the gate voltage versus channel surface potential equation. The result is an exact analytical solution of the channel surface potential as an explicit function of the gate voltage for either n or p channel operation. Additionally an approximate but highly accurate analytical solution is presented which is continuously valid for all regions of operation. Secondly, we propose a new unambiguous analytical definition for the threshold voltage of these undoped-body devices. This definition overcomes the impossibility of using the traditional definition based on the bulk Fermi potential, and the ambiguities introduced by other definitions. The threshold voltage is mathematically described also using the Lambert W function at the transition point from subthreshold to superthreshold behavior. An approximation for the )1 branch of the Lambert W function is proposed to express the threshold voltage approximately using elementary logarithmic functions. These new descriptions are then verified against two-dimensional numerical device simulations. 2003 Elsevier Ltd. All rights reserved.

Semiconductor integrated circuits with power reduction mechanism

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs

Abstract: The subthreshold swing and threshold voltage characteristics of multiple-gate SOI transistors have been numerically simulated. These devices behave like cylindrical, surrounding gate devices, with the exception of the corner inversion effect. The corner inversion effect is, however, shown to be negligible if the devices are fully depleted devices or if the gate insulator thickness is small enough.

Temperature dependence of gate–leakage current in AlGaN/GaN high-electron-mobility transistors

Abstract: We report on the studies of the temperature dependence of gate–leakage current in AlGaN/GaN high-electron-mobility transistors (HEMTs) for the temperature range 20–400 °C. The results show that the temperature dependence of gate–leakage current for AlGaN/GaN HEMTs at subthreshold regime (VGS=−6.5 V) have both negative and positive trends. It has been observed that the leakage current decreases with the temperature up to 80 °C. Above 80 °C, the leakage current increases with the temperature. The negative temperature dependence of leakage current with the activation energy +0.61 eV is due to the impact ionization. The positive temperature dependence of leakage current with the activation energy −0.20 eV is due to the surface related traps, and the activation energy −0.99 eV is due to the temperature assisted tunneling mechanism. The drain voltage at a fixed drain–leakage current reveals the occurrence of both positive (+0.28 V/K) and negative (−0.53 V/K) temperature coefficients.

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

Abstract: Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si/sub 0.7/Ge/sub 0.3/ on an Si/sub 0.85/Ge/sub 0.15/ virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process.

A low-power wide dynamic range envelope detector

Abstract: We report a 75-dB 2.8-/spl mu/W 100-Hz-10-kHz envelope detector in a 1.5-/spl mu/m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7-V/sub pp/ input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.

Electrostatics of coaxial Schottky-barrier nanotube field-effect transistors

Abstract: Analytical and numerical methods are used to solve Poisson's equation for carbon nanotube field-effect transistors (FETs) with a cylindrical surrounding gate and Schottky-barrier contacts to the source and drain. The effect on the nanotube potential profile of varying the work functions of all the electrodes, and the thickness and permittivity of the gate dielectric, is investigated. From these results, the general trends to be expected in the above-threshold drain current-voltage characteristics of Schottky-barrier nanotube FETs are predicted. The unusual possibility of simultaneous electron and hole contributions to the drain current is revealed. The subthreshold characteristics are computed from a solution to Laplace's equation, and the subthreshold slope is found to depend on gate dielectric thickness in a different manner from that in other FETs.

An SOI 4 transistors self-refresh ultra-low-voltage memory cell

Abstract: Analog and digital subthreshold circuit design have been investigated recently in some niche applications where performance is of secondary concern but ultra-low-power is needed. In this paper we propose a new four transistors self-refresh memory cell operating in the subthreshold region. Our simulations using a partially depleted SOI 0.25/spl mu/m technology show a good stability of the cell to process and temperature variations. Combining our memory cell with a current sensing scheme and grounded bit-lines leads to good performance despite a very low supply voltage.

Nanosignal processing: Stochastic resonance in carbon nanotubes that detect subthreshold signals

Abstract: Experiments confirm that small amounts of noise help a nanotube transistor detect noisy subthreshold electrical signals. Gaussian, uniform, and impulsive (Cauchy) noise produced this feedforward stochastic-resonance effect by increasing both the nanotube system’s mutual information and its input-output correlation. The noise corrupted a synchronous Bernoulli or random digital sequence that fed into the thresholdlike nanotube transistor and produced a Bernoulli sequence. Both Shannon’s mutual information and correlation measured the performance gain by comparing the input and output sequences. This nanotube SR effect was robust: it persisted even when infinite-variance Cauchy noise corrupted the signal stream. Such noise-enhanced signal processing at the nanolevel promises applications to signal detection in wideband communication systems and biological and artificial neural networks. Noise can help carbon nanotube transistors detect subthreshold electrical signals by increasing the transistor’s input output mutual information or correlation. Several researchers have demonstrated the stochastic resonance (SR) effect for various types of threshold units or neurons. 1-6 Experiments