Showing papers on "Tunnel field-effect transistor published in 2017"

A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance

Abstract: To suppress the ambipolar behavior and improve RF performance in tunnel field-effect transistors (TFETs), a Z-shaped (ZS)-TFET is proposed. The proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs and provides higher ON-state current ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}$ ), larger ON/OFF current ratio ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}/{I} _{ {\mathrm{\scriptscriptstyle OFF}}}$ ) and lower subthreshold swing compared to conventional TFETs. These advantages stem from the tunneling junction in the ZS-TFET being perpendicular to the channel direction, which facilitates the formation of a relatively large tunneling junction area. The ZS body makes use of both vertical and horizontal fields while suppressing the lateral parasitic tunneling current. In addition, by using a ZS gate in the proposed device, the energy band diagram near the source is modulated to create an N+ source pocket which creates a downward band bending of the potential, similar to PNPN-like structures. Finally, the proposed structure significantly improves the analog/RF figure-of-merit.

Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

Abstract: In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track-and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage.

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Abstract: Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current ($$I_{\mathrm{ON}}$$ION) and OFF-current ($$I_{\mathrm{OFF}}$$IOFF) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high $$I_{\mathrm{ON}}$$ION and low $$I_{\mathrm{OFF}}$$IOFF current. The impact of work function variations and doping on device performance is also comprehensively investigated.

Double gate symmetric tunnel FET: investigation and analysis

Abstract: In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF-state current and subthreshold swing (SS) are significantly high for the double gate Ge source/drain symmetric p-n-p tunnel field effect transistor (TFET) with a silicon channel without n + pockets at the source- and drain-channel interfaces. They further establish that using $n^{+}$n+ pockets at the source- and drain-channel interface, the Ge source/drain symmetric p-n-p TFET exhibits a 130 times improvement in I ON / I OFF ratio and a 26% reduction in SS due to the two orders of magnitude reduction in its OFF-state current when compared with the one without the n + pockets. The results also indicate that the Ge source/drain symmetric p-n-p TFET suffers from a low output conductance at low drain voltages. Since the proposed device exhibits bidirectional current flow, it can be easily integrated with the conventional complementary metal-oxide semiconductor technology.

Impact of Band-Tails on the Subthreshold Swing of III-V Tunnel Field-Effect Transistor

Abstract: We present a simple model to evaluate the sharpness of the band edges for tunnel field-effect transistors (TFETs) by comparing the subthreshold swing and the conductance in the negative differential resistance region. This model is evaluated using experimental data from InAs/InGaAsSb/GaSb nanowire TFETs with the ability to reach a subthreshold swing well below the thermal limit. A device with the lowest subthreshold swing, 43 mV/decade at 0.1 V, exhibits also the sharpest band-edge decay parameter ${E}_{{0}}$ of 43.5 mV although in most cases the ${S} \ll {E}_{{0}}$ . The model explains the observed temperature dependence of the subthreshold swing.

The effect of density-of-state tails on band-to-band tunneling: Theory and application to tunnel field effect transistors

Abstract: It is demonstrated how band tail states in the semiconductor influence the performance of a Tunnel Field Effect Transistor (TFET). As a consequence of the smoothened density of states (DOS) around the band edges, the energetic overlap of conduction and valence band states occurs gradually at the onset of band-to-band tunneling (BTBT), thus degrading the sub-threshold swing (SS) of the TFET. The effect of the band tail states on the current-voltage characteristics is modelled quantum-mechanically based on the idea of zero-phonon trap-assisted tunneling between band and tail states. The latter are assumed to arise from a 3-dimensional pseudo-delta potential proposed by Vinogradov [1]. This model potential allows the derivation of analytical expressions for the generation rate covering the whole range from very strong to very weak localization of the tail states. Comparison with direct BTBT in the one-band effective mass approximation reveals the essential features of tail-to-band tunneling. Furthermore, an analytical solution for the problem of tunneling from continuum states of the disturbed DOS to states in the opposite band is found, and the differences to direct BTBT are worked out. Based on the analytical expressions, a semi-classical model is implemented in a commercial device simulator which involves numerical integration along the tunnel paths. The impact of the tail states on the device performance is analyzed for a nanowire Gate-All-Around TFET. The simulations show that tail states notably impact the transfer characteristics of a TFET. It is found that exponentially decaying band tails result in a stronger degradation of the SS than tail states with a Gaussian decay of their density. The developed model allows more realistic simulations of TFETs including their non-idealities.

Dual metal drain Ge-source dopingless TFET with enhanced turn-ON steep subthreshold swing and high ON-current

Abstract: A novel dopingless Ge-source dual metal drain double gate tunnel field effect transistor is presented with the help of work function engineering Proposed device makes use of the dopingless concept, charge plasma for carrier doping concentration below the drain/source region that permits dynamic configuration by choosing suitable work function for drain/source metal electrode In the proposed device, the n + drain region is divided into two parts of low and high work function The work function of the metal nearest to the drain–channel junction is relatively higher than the other metal for creating a potential barrier for restricting the tunnelling of holes when the negative gate voltage is applied By using low energy bandgap Ge material, the tunnelling probability and drive current of the device are increased The proposed device offers high I ON/I OFF ratio (∼1013), smaller point subthreshold swing (SS) (∼31 mV/decade), average SS (∼43 mV/decade)

Trap-Tolerant Device Geometry for InAs/Si pTFETs

Abstract: The influence of channel quantization and interface traps on the performance of InAs/Si pTFETs is analyzed, and a device geometry is predicted which is least sensitive to trap-assisted tunneling (TAT). The good agreement between simulated and measured transfer characteristics validates the reliability of the simulation setup. Simulations show that TAT degrades the sub-threshold swing (SS) of the tunnel field effect transistor (TFET) and that channel quantization reduces its ON-current. The same simulation setup is used to find the device geometry which is least susceptible to interface traps. Scaling down the nanowire diameter below 20 nm inhibits TAT at the oxide/InAs interface. Furthermore, aligning the gate edge with the InAs/Si hetero-junction reduces the degradation of the SS caused by TAT at the hetero-interface. In this way, a gate-aligned InAs/Si nanowire TFET with diameter ~20 nm can deliver sub-thermal sub-threshold swing even in the unavoidable presence of oxide- and hetero-interface traps.

An Algorithm for Extraction of Threshold Voltage in Heterojunction TFETs

Abstract: This paper presents and validates an algorithm based on two-dimensional Poisson's Equation, and proposed “tangents on surface potential plots” approach to extract threshold voltage in a silicon tunnel field effect transistor (TFET) with a SiGe layer at tunnel junction. The approach stands valid for homojunction Silicon TFET and SiGe channel Silicon TFET.

Impact of device engineering on analog/RF performances of tunnel field effect transistors

Abstract: The tunnel field effect transistor (TFET) and its analog/RF performance is being aggressively studied at device architecture level for low power SoC design. Therefore, in this paper we have investigated the influence of the gate-drain underlap (UL) and different dielectric materials for the spacer and gate oxide on DG-TFET (double gate TFET) and its analog/RF performance for low power applications. Here, it is found that the drive current behavior in DG-TFET with a UL feature while implementing dielectric material for the spacer is different in comparison to that of DG-FET. Further, hetero gate dielectric-based DG-TFET (HGDG-TFET) is more resistive against drain-induced barrier lowering (DIBL) as compared to DG-TFET with high-k (HK) gate dielectric. Along with that, as compared to DG-FET, this paper also analyses the attributes of UL and dielectric material on analog/RF performance of DG-TFET in terms of transconductance (gm ), transconductance generation factor (TGF), capacitance, intrinsic resistance (Rdcr), cut-off frequency (F T), and maximum oscillation frequency (F max). The LK spacer-based HGDG-TFET with a gate-drain UL has the potential to improve the RF performance of device.

A First Insight to the Thermal Dependence of the DC, Analog and RF Performance of an S/D Spacer Engineered DG-Ambipolar FET

Abstract: This paper investigates for the first time the temperature dependence of the digital/analog parameters and RF figure of merits (FOMs) of a spacer based reconfigurable field-effect transistor (RFET) and compares the same with the existing RFET topology and other devices which depend on band-to-band tunneling (BTBT) for their on-current generation. It is observed that the output characteristics of the device are less sensitive to the temperature in the BTBT dominated on-state region as compared to the subthreshold one which is thermionic emission dependent. Having a better thermal stability over tunnel field effect transistor (TFET) and significantly lesser Vth roll-off, the proposed device portrays orders of magnitude reduction in parasitic gate capacitances and intrinsic delay as compared to gate-all-around (GAA) and hetero gate dielectric GAA TFET devices over the considered range of temperature, thus assuring higher switching speed for digital applications. Moreover, superior analog/RF performance is also exhibited by the device under consideration for all temperatures in contrast to SiGe, full silicon TFETs, and conventional RFET topology owing to higher BTBT dominance and better gate controllability. Apart from all of these performance gains, the device FOMs are found to be less sensitive to temperature variations making it more suitable for applications where temperature fluctuation is a major concern.

Introduction of a metal strip in oxide region of junctionless tunnel field-effect transistor to improve DC and RF performance

Abstract: Achieving steeper subthreshold slope and high ON–OFF current ratio ( $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ) is essential for use of semiconductor devices in switching applications. It is well known that tunnel field-effect transistors face serious issues related to low ON-state current and poor radio frequency (RF) response. We report herein a unique method for realizing a sharp tunneling junction in a charge plasma-based junctionless tunnel field-effect transistor by embedding a metal strip in the oxide region near to the source–channel connection. This modulates the carrier concentration profile at the source–channel interface, making it abrupt. This steeper source–channel tunneling junction results in a reduced tunneling barrier and increased flow of charge carriers at the junction. Furthermore, electron transfer along the channel is accounted for using postprocessing based on the drift–diffusion equations as well as the band-to-band tunneling current. This phenomenon contributes to the improved direct-current (DC) characteristics of the device. Selection of a metal with an appropriate work function for the strip can improve the subthreshold swing and threshold voltage ( $$V_{\mathrm{th}}$$ ) of the device. The increased charge carrier tunneling rate at the junction also results in a huge improvement in RF parameters of the device, including cutoff frequency ( $$f_{T}$$ ), gain–bandwidth product, and transit time ( $$\tau $$ ).

Band-to-band tunneling in Γ valley for Ge source lateral tunnel field effect transistor: Thickness scaling

Abstract: The direct and indirect valleys in Germanium (Ge) are separated by a very small offset, which opens up the prospect of direct tunneling in the Γ valley of an extended Ge source tunnel field effect transistor (TFET). We explore the impact of thickness scaling of extended Ge source lateral TFET on the band to band tunneling (BTBT) current. The Ge source is extended inside the gate by 2 nm to confine the tunneling in Ge only. We observe that as the thickness is scaled, the band alignment at the Si/Ge heterojunction changes significantly, which results in an increase in Ge to Si BTBT current. Based on density functional calculations, we first obtain the band structure parameters (bandgap, effective masses, etc.) for the Ge and Si slabs of varying thickness, and these are then used to obtain the thickness dependent Kane's BTBT tunneling parameters. We find that electrostatics improves as the thickness is reduced in the ultra-thin Ge film ( ≤ 10 nm). The ON current degrades as we scale down in thickness; howeve...

Temperature based performance analysis of doping-less tunnel field effect transistor

Abstract: Recently, the doping-less Tunnel Field Effect Transistor (TFET) has emerged as a novel device for the replacement of conventional TFET due to its similar trend in current characteristics and reduced fabrication complexity with low cost. However, the impact of temperature on its performance is yet an undiscovered aspect. The semiconductor devices are known to have significant temperature dependence characteristics. Thus, it is very much of importance to analyse the behavior of the device at different temperature. In this concern, an extensive study has been performed for temperature sensitivity analysis of the behavior of the doping-less TFET. For this, transfer characteristics, energy band diagram and carrier concentration are considered as DC figure of merits, whereas Transconductance (gm), gate-to-drain capacitance (Cgd)), cut off frequency (fT) and gain bandwidth product (GBW) are used as RF performance parameters. Further, the effect of variation in temperature on the Off-state and its components such as Band to Band Tunneling (BTBT), Trap Assisted Tunneling (TAT) and Shockley-Read-Hall (SRH) is also analyzed with different drainchannel spacer widths for doping-less TFET. All the simulations have been performed on Silvaco ATLAS simulator.

Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure

Abstract: A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson's equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry*

Abstract: In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device.

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability.

Abstract: The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ~1.2 μA μm−1 along with a longer retention time (RT) of ~1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges

Abstract: Tunneling field effect transistors (TFETs) are playing a pivotal role in the unhindered progress of microelectronics industry into sub-micron and nanometer regime by efficiently replacing conventional MOSFETs by dint of their superior performance at such a low device dimension. In this research endeavor, we have incorporated the innovative gate engineering concept of continuously varying mole fraction in a binary metal alloy (BMA) gate electrode along the horizontal direction into a conventional TFET on buried oxide layer. The proposed BMA silicon-on-nothing (BMASON) TFET helps to tune the barrier at the source-channel junction, so that the band-to-band tunneling of the carriers occurs at a significant rate, thereby increasing the device ON current. However, device operation at such ultralow dimension will result in a considerably high electric field which inevitably impacts device performance due to hot carrier effect-induced localized charge trapping in the oxide region. This work presents an analytical model based on the Poisson’s equation and the Kane’s model incorporating the localized trapped charges at the oxide–silicon interface to explore the impact of localized charges on the performance of the proposed BMASON TFET in terms of surface potential, electric field and drain current characteristics. To validate our proposed model we have compared the results with 2D Sentaurus TCAD data and found good agreement between the two, thereby making this model suitable to design future charge-trapped memory devices based on TFET operation.

Surface potential based modeling of charge, current, and capacitances in DGTFET including mobile channel charge and ambipolar behaviour

Abstract: We present a surface potential based analytical model for double gate tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the inverse decay length, which is constant under channel depletion condition and bias dependent under inversion condition. To capture the ambipolar current behavior in the model, tunneling at the drain junction is also included. The proposed model is validated against TCAD simulation data and it shows close match with the simulation data.