Journal ArticleDOI
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TLDR
In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.Abstract:
A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.read more
Citations
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Journal ArticleDOI
Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications
TL;DR: A stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation for ultra-low-power (LP) applications and demonstrates a sub-10 nm LP switching device that realizes a good S and lower Ioff at a lower supply voltage (VDD) of 0.2 V.
Design and Optimization of A P+N+IN+ Tunnel FET
TL;DR: The width and the doping level of n+ δ-doped region are optimized aiming at increasing the Ion/Ioff ratio and improving the output characteristics andSimulations show that the proposed transistor exhibits Ion/ Ioff ratio as high as 10.5%, much like a MOSFET.
Proceedings ArticleDOI
Analytical approach to consider Gaussian junction profiles in compact models of tunnel-FETs
TL;DR: In this paper, the impact of Gaussian-shaped doping profiles on the potential and the current transfer characteristics of an Double-Gate (DG) Tunnel-FET (TFET) is investigated.
Journal ArticleDOI
Quantum simulation study of double gate hetero gate dielectric and LDD doping graphene nanoribbon p–i–n tunneling FETs
TL;DR: In this paper, the effects of the lightly doped drain (LDD) and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors (TFETs) are investigated.
Proceedings ArticleDOI
Performance Analysis of Double Gate Heterojunction Tunnel Field Effect Transistor
TL;DR: In this paper, the performance of various TFET devices like Single gated, Double gated TFET, Homojunction and Heterojunction has been compared in terms of I ON /I OFF ratio and subthreshold swing parameters.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Zener tunneling in semiconductors
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
Journal ArticleDOI
Complementary tunneling transistor for low power application
Peng-Fei Wang,K. Hilsenbeck,Th. Nirschl,M. Oswald,Ch. Stepper,M. Weis,Doris Schmitt-Landsiedel,Walter Hansch +7 more
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Journal ArticleDOI
Silicon surface tunnel transistor
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
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