Journal ArticleDOI
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TLDR
In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.Abstract:
A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.read more
Citations
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Proceedings ArticleDOI
Design of digital standard cell based on silicon tunnel field-effect transistor
TL;DR: This experiment contains the principle and characteristic of the Tunnel FETs, and specific standard cell circuit design based on the given model, and the result of the simulation finds that TFET devices' speed is slower than MOS devices, but the power consumption can reduce to less than 10% of the same size MOS device.
Journal ArticleDOI
Device physics and design of symmetrically doped tunnel field-effect transistors
TL;DR: In this paper, the authors investigated the device physics and design of point-tunneling TFETs with symmetric doping profiles and showed that the on-current is doubled due to an additional source and the ambipolar off-leakage is significantly diminished because the drain tunnel junction is designed far from the gate.
Proceedings ArticleDOI
Impact of diameter on TFET conduction mechanisms
TL;DR: In this paper, the impact of diameter on the TFET conduction mechanisms and the consequent influence on the device performance was investigated through simulation analysis, and the results showed a higher current level and a lower gate voltage to reach the band-to-band tunneling regime in NW-TFETs with smaller diameters.
Proceedings ArticleDOI
Design of 3D cylindrical GAA-TFET based on germanium source with drain underlap for low power applications
TL;DR: In this article, a cylindrical GAA TFET based on germanium source was proposed for low power applications. But the proposed device used the merits of low band gap material, which is used as a material in the source region, and it showed the better device performance to address the requirement of ultra-low power applications, which corresponds to 7 × improvement in I ON /I OFF ratio when compared with the Si-GAA-TFET.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Zener tunneling in semiconductors
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
Journal ArticleDOI
Complementary tunneling transistor for low power application
Peng-Fei Wang,K. Hilsenbeck,Th. Nirschl,M. Oswald,Ch. Stepper,M. Weis,Doris Schmitt-Landsiedel,Walter Hansch +7 more
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Journal ArticleDOI
Silicon surface tunnel transistor
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
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