Journal ArticleDOI
Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
TLDR
In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.Abstract:
A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.read more
Citations
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Journal ArticleDOI
Impact of source pocket doping on RF and linearity performance of a cylindrical gate tunnel FET
TL;DR: In this paper, a cylindrical gate tunnel (CGT) field effect transistors (FETs) with a highly doped pocket layer introduced in the source region is presented.
Journal ArticleDOI
Design optimisation of junctionless TFET biosensor for high sensitivity
Journal ArticleDOI
FinFET based SRAMs in Sub-10nm domain
TL;DR: This review paper presents different types of SRAM bitcells and memory system architectures and presents a benchmarking between the Underlapped FinFET based SRAM and Design Technology Optimized FinFet Based SRAM to determine the robustness ofSRAM designs.
Journal ArticleDOI
Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor
TL;DR: In this article, the effects of variation in different structural parameters of a gate-on-germanium source (GoGeS) tunnel field effect transistor (TFET) on its electrical performance were investigated.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Zener tunneling in semiconductors
TL;DR: In this paper, the Zener current in a constant field is calculated both with and without the W annier -A dams reduction of the interband-coupling terms, interpreted as a polarization correction.
Journal ArticleDOI
Complementary tunneling transistor for low power application
Peng-Fei Wang,K. Hilsenbeck,Th. Nirschl,M. Oswald,Ch. Stepper,M. Weis,Doris Schmitt-Landsiedel,Walter Hansch +7 more
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Journal ArticleDOI
Silicon surface tunnel transistor
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
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