Journal ArticleDOI
Short-Channel Effects in Tunnel FETs
Jianzhi Wu,Jie Min,Yuan Taur +2 more
TLDR
In this article, the authors investigated short-channel effects in double-gate tunnel FETs using an analytic model that includes depletion in the source and showed that the drain bias has a significant effect on the potential profile at the source when the channel length is reduced to below twice the scale length.Abstract:
This paper investigates short-channel effects (SCEs) in double-gate tunnel FETs (TFETs) using an analytic model that includes depletion in the source. It is shown that the drain bias has a significant effect on the potential profile at the source when the channel length is reduced to below twice the scale length. The OFF-state current becomes a strong function of channel length. The subthreshold current slope is also degraded in short-channel TFETs to the extent that there is no region of <60 mV/decade below a minimum channel length. The SCE also manifests itself in the finite-output conductance in the saturation region—a Drain-Induced Barrier Lowering-like effect in conventional MOSFETs.read more
Citations
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Journal ArticleDOI
Schottky Tunneling Effects in a Tunnel FET
TL;DR: The influence of junction extension length on TFET behavior is discussed where the length of the gate spacer is assumed to be the gap between the source and drain (S/D) electrodes and the gate edge, and the device performance of a TFET with higher source-side doping concentrations can be further improved even at the aggressively scaled-down level.
Journal ArticleDOI
Performance of differential pair circuits designed with line tunnel FET devices at different temperatures
Journal ArticleDOI
Performance Analysis of Hetero Gate Oxide with Work Function Engineering Based SC-TFET with Impact of ITCs
Journal ArticleDOI
DC performance analysis of III–V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon FET circuits with quantum mechanical effects
TL;DR: In this article, the electrical behavior of laterally grown novel short-channel III-V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) has been studied based on their quantum mechanical effect.
Dissertation
Characterization of TFETs made using a Low-Temperature process and innovative TFETs architectures for 3D integration
TL;DR: In this paper, a study of FDSOI tunnel FETs from planar to trigate/nanowire structures is presented, where functional low-temperature TFETs are fabricated with low-thermal budget (630°C) process flow, specifically designed for top tier devices in 3D sequential integration.
References
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Journal ArticleDOI
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Alan Seabaugh,Qin Zhang +1 more
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Book
Fundamentals of carrier transport
TL;DR: The fundamental principles of carrier transport in semiconductors and semiconductor devices are discussed in this article, which is an accessible introduction to the behavior of charged carriers in semiconductor and semiconductor devices.
Journal ArticleDOI
A continuous, analytic drain-current model for DG MOSFETs
TL;DR: In this article, a continuous analytic currentvoltage model for double-gate MOSFETs is presented, which is derived from closed-form solutions of Poisson's equation, and current continuity equation without the charge-sheet approximation.
Journal ArticleDOI
Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs
TL;DR: In this paper, a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field effect transistors (TFETs) is presented, using semiconducting carbon nanotubes as the model channel material.
Journal ArticleDOI
Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs
TL;DR: In this paper, a simple but powerful evanescent-mode analysis showed that the length /spl lambda/ over which the source and drain perturb the channel potential, is 1/spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the cylindrical case, in excellent agreement with PADRE device simulations.