Showing papers on "Digital electronics published in 2007"

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Abstract: Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 X higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 X 132 mum2test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 mus measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.

Evolvable systems : from biology to hardware : 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007 : proceedings

Abstract: Digital Hardware Evolution.- An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification.- Design of Electronic Circuits Using a Divide-and-Conquer Approach.- Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel.- An Intrinsic Evolvable Hardware Based on Multiplexer Module Array.- Estimating Array Connectivity and Applying Multi-output Node Structure in Evolutionary Design of Digital Circuits.- Research on the Online Evaluation Approach for the Digital Evolvable Hardware.- Research on Multi-objective On-Line Evolution Technology of Digital Circuit Based on FPGA Model.- Evolutionary Design of Generic Combinational Multipliers Using Development.- Analog Hardware Evolution.- Automatic Synthesis of Practical Passive Filters Using Clonal Selection Principle-Based Gene Expression Programming.- Research on Fault-Tolerance of Analog Circuits Based on Evolvable Hardware.- Analog Circuit Evolution Based on FPTA-2.- Bio-inspired Systems.- Knowledge Network Management System with Medicine Self Repairing Strategy.- Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance.- Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.- Bio-inspired Systems with Self-developing Mechanisms.- Development of a Tiny Computer-Assisted Wireless EEG Biofeedback System.- Steps Forward to Evolve Bio-inspired Embryonic Cell-Based Electronic Systems.- Evolution of Polymorphic Self-checking Circuits.- Mechanical Hardware Evolution.- Sliding Algorithm for Reconfigurable Arrays of Processors.- System-Level Modeling and Multi-objective Evolutionary Design of Pipelined FFT Processors for Wireless OFDM Receivers.- Reducing the Area on a Chip Using a Bank of Evolved Filters.- Evolutionary Design.- Walsh Function Systems: The Bisectional Evolutional Generation Pattern.- Extrinsic Evolvable Hardware on the RISA Architecture.- Evolving and Analysing "Useful" Redundant Logic.- Adaptive Transmission Technique in Underwater Acoustic Wireless Communication.- Autonomous Robot Path Planning Based on Swarm Intelligence and Stream Functions.- Research on Adaptive System of the BTT-45 Air-to-Air Missile Based on Multilevel Hierarchical Intelligent Controller.- The Design of an Evolvable On-Board Computer.- Evolutionary Algorithms in Hardware Design.- Extending Artificial Development: Exploiting Environmental Information for the Achievement of Phenotypic Plasticity.- UDT-Based Multi-objective Evolutionary Design of Passive Power Filters of a Hybrid Power Filter System.- Designing Electronic Circuits by Means of Gene Expression Programming II.- Designing Polymorphic Circuits with Evolutionary Algorithm Based on Weighted Sum Method.- Robust and Efficient Multi-objective Automatic Adjustment for Optical Axes in Laser Systems Using Stochastic Binary Search Algorithm.- Minimization of the Redundant Sensor Nodes in Dense Wireless Sensor Networks.- Evolving in Extended Hamming Distance Space: Hierarchical Mutation Strategy and Local Learning Principle for EHW.- Hardware Implementation of Evolutionary Algorithms.- Adaptive and Evolvable Analog Electronics for Space Applications.- Improving Flexibility in On-Line Evolvable Systems by Reconfigurable Computing.- Evolutionary Design of Resilient Substitution Boxes: From Coding to Hardware Implementation.- A Sophisticated Architecture for Evolutionary Multiobjective Optimization Utilizing High Performance DSP.- FPGA-Based Genetic Algorithm Kernel Design.- Using Systolic Technique to Accelerate an EHW Engine for Lossless Image Compression.

Digital Design and Computer Architecture

Abstract: "Digital Design and Computer Architecture" takes a unique and modern approach to digital design. Beginning with digital logic gates and progressing to the design of combinational and sequential circuits, Harris and Harris use these fundamental building blocks as the basis for what follows: the design of an actual MIPS processor. SystemVerilog and VHDL are integrated throughout the text in examples illustrating the methods and techniques for CAD-based circuit design. By the end of this book, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works. Harris and Harris have combined an engaging and humorous writing style with an updated and hands-on approach to digital design. This second edition has been updated with new content on I/O systems in the context of general purpose processors found in a PC as well as microcontrollers found almost everywhere. The new edition provides practical examples of how to interface with peripherals using RS232, SPI, motor control, interrupts, wireless, and analog-to-digital conversion. High-level descriptions of I/O interfaces found in PCs include USB, SDRAM, WiFi, PCI Express, and others. In addition to expanded and updated material throughout, SystemVerilog is now featured in the programming and code examples (replacing Verilog), alongside VHDL. This new edition also provides additional exercises and a new appendix on C programming to strengthen the connection between programming and processor architecture. It covers the fundamentals of digital logic design and reinforces logic concepts through the design of a MIPS microprocessor. It features side-by-side examples of the two most prominent Hardware Description Languages (HDLs)-SystemVerilog and VHDL - which illustrate and compare the ways each can be used in the design of digital systems. It includes examples throughout the text that enhance the reader's understanding and retention of key concepts and techniques. Companion Web site includes links to CAD tools for FPGA design from Altera and Mentor Graphics, lecture slides, laboratory projects, and solutions to exercises. Updated based on instructor feedback with more exercises and new examples of parallel and advanced architectures, practical I/O applications, embedded systems, and heterogeneous computing. It presents digital system design examples in both VHDL and SystemVerilog (updated for the second edition from Verilog), shown side-by-side to compare and contrast their strengths. It includes a new chapter on C programming to provide necessary prerequisites and strengthen the connection between programming and processor architecture. Instructors can also register at textbooks.elsevier.com for access to: solutions to all exercises (PDF); lab materials with solutions; HDL for textbook examples and exercise solutions; Lecture slides (PPT); Sample exams\ Sample course syllabus; and figures from the text (JPG, PPT).

Optics inspired logic architecture

Abstract: Conventional architectures for the implementation of Boolean logic are based on a network of bistable elements assembled to realize cascades of simple Boolean logic gates. Since each such gate has two input signals and only one output signal, such architectures are fundamentally dissipative in information and energy. Their serial nature also induces a latency in the processing time. In this paper we present a new, principally non-dissipative digital logic architecture which mitigates the above impediments. Unlike traditional computing architectures, the proposed architecture involves a distributed and parallel input scheme where logical functions are evaluated at the speed of light. The system is based on digital logic vectors rather than the Boolean scalars of electronic logic. The architecture employs a novel conception of cascading which utilizes the strengths of both optics and electronics while avoiding their weaknesses. It is inherently non-dissipative, respects the linear nature of interactions in pure optics, and harnesses the control advantages of electrons without reducing the speed advantages of optics. This new logic paradigm was specially developed with optical implementation in mind. However, it is suitable for other implementations as well, including conventional electronic devices.

NBTI-aware synthesis of digital circuits

Abstract: Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel method to characterize the delay of every gate in the standard cell library, as a function of the signal probability of each of its inputs, is developed. Accordingly, a technology mapping technique that incorporates the NBTI stress and recovery effects, in order to ensure optimal performance of the circuit, during its entire lifetime, is presented. Our technique, demonstrated over 65 nm benchmarks shows an average of 10 % area recovery, and 12 % power savings, as against a pessimistic method that assumes constant stress on all PMOS transistors in the design.

Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits

Abstract: Scaling of silicon transistors continue in the sub 100-nm regime amidst severe roadblocks. Increased short-channel effects, rising leakage currents, severe process parameter variations are only a few of the overwhelming challenges that the device and circuit designers are faced with. In an attempt to alleviate the problems associated with the scaling of silicon transistors, researchers have began a quest for novel alternate materials in a post-Si nanoelectronics era. Of the different materials investigated so far, carbon nanotubes with their superior transport properties, excellent thermal conductivities and high current handling capacities have proved to be a potential heir to Si. This paper reviews the promise of carbon nanotube field-effect transistors as future devices for high-performance as well as low-power electronics.

Designing Electronic Circuits Using Evolutionary Algorithms. Arithmetic Circuits: A Case Study

Abstract: A Genetic Algorithm is presented which is capable of evolving 100% functional arithmetic circuits. Evolved designs are presented for one-bit, two-bit adders with carry, and two and three-bit multipliers and details of the 100% correct evolution of three and four-bit adders. The largest of these circuits are the most complex digital circuits to have been designed by purely evolutionary means. The algorithm is able to re-discover conventionally optimum designs for the one-bit and two-bit adders, but more significantly is able to improve on the conventional designs for the two-bit multiplier. By analysing the history of an evolving design up to complete functionality it is possible to gain insight into evolutionary process. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells and is modelled on the resources available on the Xilinx 6216 FPGA device. Further work is described about plans to evolve the designs directly onto this device.

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

Abstract: In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

MOS-Based Spin Devices for Reconfigurable Logic

Abstract: Semiconductor-based spin transistors are expected to give a new spin degree of freedom in future electronics. While many different spin transistors have been proposed and studied, the spin MOSFET is one of the most promising devices, because it can have spin-dependent output characteristics, transistor functions, and good compatibility with existing silicon technology. The device concept, structures of various types of spin MOSFETs, operation principles, calculated output characteristics, and applications was reviewed. It is shown that the output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the two ferromagnetic layers in the device, that is, high current-drive capability in parallel magnetization and low current-drive capability in antiparallel magnetization. Furthermore, nonvolatile memory and reconfigurable logic gates was presented using spin MOSFETs, where the logic functions can be changed by switching their magnetization configurations. Circuit design and numerical simulations of reconfigurable gates for NAND/NOR, AND/OR, and all symmetric Boolean functions was shown

Digital circuit arrangements for ambient noise-reduction

Abstract: The invention provides a digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible, through the use of a low latency signal processing chain consisting of analogue-to-digital conversion, digital processing and digital-to-analogue conversion. The arrangement converts the analogue signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.

Position Measurement in Industrial Drives by Means of Low-Cost Resolver-to-Digital Converter

Abstract: A fully integrated board for resolver-to-digital conversion is proposed in this paper. It is based on a combined analog/digital circuit, which allows one to track the shaft angle of a standard resolver in a digital form. Furthermore, the board also provides the feeding signal for the resolver-rotor circuit. All the tuning and configuration settings, which allow one to adapt different kind of resolvers to the proposed system, can be easily implemented directly on the board. The final assembly is a compact low-cost resolver-to-digital converter. The entire board design and implementation are described in this paper. In addition, several tests at different resolver speeds have been performed for validation.

Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network

Abstract: In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes The dummy transistors are in an OFF state all the time The gate length of each of the dummy gate electrodes is extended over an end portion of a diffusion region toward the inside of the standard cell Thus, the total surface area and the total perimeter of respective gate electrodes of all transistors provided in the standard cell are increased As a result, for example, even though shapes of gate electrodes of transistors vary between the standard cell and each of other standard cells, transistor characteristics are substantially equal among the standard cells Therefore, variations in delays of signals generated between the standard cells can be suppressed

20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

Abstract: Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA/cm2 Nb/AlOx/Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoNx resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 mum; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of rapid single flux quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of plusmn13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Abstract: Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

Abstract: This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

FPGA-Based Power Measuring for Induction Heating Appliances Using Sigma–Delta A/D Conversion

Abstract: This paper presents a field-programmable gate array (FPGA) implementation of a digital circuit that measures in real time the output power of medium-frequency (25-50 kHz) induction-heated cooking appliances. The voltage and current are sensed using first-order sigma-delta (SigmaDelta) analog-to-digital converters. The power-measuring algorithm is very simple while maintaining good accuracy. The algorithm is developed using a hardware description language (VHDL). The digital circuit, the power converter, the signal conditioning circuits, and the SigmaDelta modulators are simulated all together using a mixed-signal (analog + digital) simulation tool. The algorithm error is obtained in simulation computing the average power using VHDL-Analog and Mixed-Signal Extension Language (VHDL-AMS), and the influence of different parameters is analyzed. Finally, the digital circuit is implemented in the FPGA, and the simulations are experimentally verified.

Bitwise Competition Logic for compact digital comparator

Abstract: In this paper, we present a bitwise competition logic (BCL) for the high performance and area efficient digital comparator It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations The detail circuits to implement BCL, pre-encoder and selection logics are explained The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality

Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing

Abstract: We have analyzed two options of using hybrid CMOS/nanodevice circuits with area-distributed (CMOL) interface for the low-level image processing tasks, on the simplest example of 2-D image convolution with a sizable filter window. The first option is to use digital, DSP-like circuits based on a reconfigurable CMOL fabric, while the second one is based on mixed-signal CMOL circuits with the analog presentation of input and output data and the binary presentation of the filter function. Estimates of the circuit performance have been carried out for the 45-nm CMOS technology and the 4.5-nm nanowire half-pitch, and the power consumption fixed at a manageable, ITRS-specified level. In the digital case, the circuit area per pixel is about 25times25 , and the time necessary for convolving a 1024times1024-pixel, 12-bit-accurate image with a 3232-pixel window function of similar accuracy is close to 25 , much shorter than that estimated for purely CMOS circuits with the same minimum feature size on 45 nm. For a mixed-signal CMOL circuit, the corresponding numbers are much better ( ~1 mum2 and 1mus, respectively), but this option requires a very high (~1%) reproducibility of on currents of the necessary crosspoint devices (programmable diodes), which has not yet been reached experimentally.

A Simulation Environment for e-Learning in Digital Design

Abstract: Deeds is a simulation environment for e-learning in digital electronics. The simulators cover combinational and sequential logic networks, finite state-machine design, and microcomputer interfacing and programming. They are integrated together, and therefore allow the design and test of embedded digital systems. The environment guides students' activities by delivering learning materials through specialized browsers. An extensive collection of learning materials is available. This paper includes an example of activity on a problem assignment.

Thresholded samplers for UWB impulse radar

Abstract: This paper presents two novel methods for sampling the backscatter in an impulse radar system. The authors have called the two related methods for swept threshold and stochastic resonance sampling. The samplers are simple, mostly digital circuits which are not clocked, but instead utilize continuous-time signal processing. Since fine-pitch CMOS is not very good for analog processing, but instead has very fast digital logic, the samplers are well suited for this technology. An implementation in 90 nm CMOS is described and measurements which confirm a working 23 GHz sampler are shown

Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design

Abstract: Data processing optimization is one of the main concerns for developing of multiple-valued logic. An advantage could be achieved by realization of new functions existing in non-binary logic. These new logic functions could be implemented using quaternary look-up tables. In this work, a quaternary multiplexer circuit is designed to implement any n-variable quaternary logic function based on its truth table. Voltage-mode CMOS with multi-threshold transistors and multi-Vdd quaternary design was suggested. The multiplexer circuit consists of quaternary down literal circuits, binary inverters and binary pass transistor gates. All circuits were simulated with the Spice tool using TSMC 0.18 mum technology and have shown improvements in performance and power consumption and using less transistors than their equivalent binary circuits.

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

Abstract: A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2psrms jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum2 in a 0.13mum CMOS process and dissipates 13.2mW from a 1.2V supply when operating at 2.5Gb/s.

A Digital CMOS Architecture for a Micro-Hotplate Array

Abstract: A monolithic gas sensor array fabricated in industrial CMOS technology combined with post-CMOS micromachining is presented. The device comprises an array of three metal-oxide-coated micro-hotplates with integrated MOS transistor heaters and the needed driving and signal-conditioning circuitry. Three digital PID controllers enable individual temperature regulation for each hotplate. The operating temperature of the SnO2 metal-oxide sensors may amount up to 350degC. A serial interface and the temperature control units have been implemented digitally. Emphasis was put on designing a modular system with the required analog circuitry reduced to a minimum. With its small overall size of 5.5times4.5 \ mm2, its digital interface and its good hotplate thermal efficiency of 6degC/mW, the system represents a significant development on the way to low-cost mobile gas sensor systems. The limit of detection at constant temperatures has been assessed to be below 1 ppm for CO and approximately 100 ppm for CH4. The mainly digital implementation with a maximum sampling rate of 9.3 kHz for all three sensors offers the advantage to apply a power-saving mode and temperature modulation techniques to enhance the analyte discrimination capability

Using synchronization to obtain dynamic logic gates.

Abstract: We introduce a scheme to obtain key logic-gate structures, using synchronization of nonlinear systems. We demonstrate the idea explicitly by numerics and experiments on nonlinear circuits. A significant feature of this scheme is that a single nonlinear drive-response circuit can be used to flexibly yield the different logic gates, and switch logic behavior by small changes in the parameter of the response system; so the response system can act as a ``logic output controller.'' Thus this scheme may help to construct dynamic general-purpose computational hardware with reconfigurable abilities.

Techniques for Random Masking in Hardware

Abstract: A new technique for Boolean random masking of the logic and operation in terms of nand logic gates is proposed and applied for masking the integer addition. The new technique can be used for masking arbitrary cryptographic functions and is more efficient than previously known techniques, recently applied to the Advanced Encryption Standard (AES). New techniques for the conversions from Boolean to arithmetic random masking and vice versa are also developed. They are hardware oriented and do not require additional random bits. Unlike the previous, software-oriented techniques showing a substantial difference in the complexity of the two conversions, they have a comparable complexity being about the same as that of one integer addition only. All the techniques proposed are in theory secure against the first-order differential power analysis on the logic gate level. They can be applied in hardware implementations of various cryptographic functions, including AES, (keyed) SHA-1, IDEA, and RC6

Multi-core architecture with hardware messaging

Abstract: Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits include processors having dedicated messaging hardware that enable processor cores to minimize interrupt activity related to inter-core communications. The messaging hardware receives and parses any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.

Exploring Very Low-Energy Logic: A Case Study

Abstract: This paper shows leakage as a limit to the effectiveness of voltage scaling as a means of reducing the energy per operation in a digital circuit. Methods of decreasing operational or dynamic leakage are then discussed. The design and simulation results of a sense amplifier-based pass transistor logic (SAPTL) circuit topology as a low leakage and low energy alternative is presented and then compared to standard static 90-nm CMOS implementations.

Principles of Modern Digital Design

Abstract: 1. Number Systems and Binary Codes. 2. Fundamental Concepts of Digital Logic. 3. Combinational Logic Design. 4. Fundamentals of Synchronous Sequential Circuits. 5. VHDL in Digital Design. 6. Combinational Logic Design using VHDL. 7. Synchronous Sequential Circuit Design. 8. Counter Design. 9. Sequential Circuit Design using VHDL. 10. Asynchronous Sequential Circuits. Appendix A. CMOS Logic. Index.

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices

Abstract: This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students.

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

Abstract: A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.