J
J. Cai
Researcher at IBM
Publications - 23
Citations - 499
J. Cai is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 10, co-authored 22 publications receiving 472 citations.
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Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Proceedings ArticleDOI
Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs
TL;DR: In this article, a novel mobility extraction technique showed that the mobility enhancements in strained Si MOSFETs were retained in deep sub-100 nm channel lengths, despite the presence of high halo doping.
Proceedings ArticleDOI
Device design considerations for ultra-thin SOI MOSFETs
Bruce B. Doris,Meikei Ieong,T. Zhu,Y. Zhang,Michelle L. Steen,Wesley C. Natzle,S. Callegari,Vijay Narayanan,J. Cai,S.H. Ku,Paul C. Jamison,Li Yulong,Z. Ren,Victor Ku,T. Boyd,Thomas S. Kanarsky,Christopher P. D'Emic,M. Newport,David M. Dobuzinsky,Sadanand V. Deshpande,J. Petrus,Rajarao Jammy,Wilfried Haensch +22 more
TL;DR: In this paper, the authors used the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel and demonstrated the first planar single gate nFET with 8 nm gate-length.
Proceedings ArticleDOI
Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs
Naoki Tega,Hiroshi Miki,Zhibin Ren,Christopher P. D'Emic,Yu Zhu,David J. Frank,J. Cai,M. Guillorn,D.-G. Park,Wilfried Haensch,Kazuyoshi Torii +10 more
TL;DR: In this paper, the reduction of random telegraph noise (RTN) in high-к / metal gate (HK / MG) stacks incorporated in 22 nm generation FETs was demonstrated.
Proceedings ArticleDOI
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
J. Cai,K. Rim,A. Bryant,Keith Jenkins,C. Ouyang,D.V. Singh,Z. Ren,Kam-Leung Lee,Haizhou Yin,John M. Hergenrother,Thomas S. Kanarsky,Amit Kumar,X. Wang,S. W. Bedell,Alexander Reznicek,Harold J. Hovel,D. K. Sadana,D. Uriarte,Ryan M. Mitchell,John A. Ott,Dan Mocuta,P. O'Neil,Anda Mocuta,Effendi Leobandung,R. J. Miller,W. Haensch,Meikei Leong +26 more
TL;DR: In this paper, the scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported, indicating strain-induced enhancement can be sustained in future technology nodes.