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Journal ArticleDOI

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

TLDR
Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field effect transistors (TFETs) is developed in this article.
Abstract
Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

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Citations
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Journal ArticleDOI

A modified pseudo 2D physically-based model for double-gate TFETs: Role of precise calculations of drain and source depletion regions

TL;DR: In this paper, a modified pseudo-two-dimensional semi-analytical model for double gate tunnel FETs is introduced, where the main regions in the DG-TFET structure are the channel and the depletion regions inside the source and the drain.
Journal ArticleDOI

A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET

TL;DR: In this paper, a charge-based capacitance model has been proposed for a double-gate (DG) hetero-gate-dielectric tunnel FET (HGD-TFET).
Journal ArticleDOI

Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

TL;DR: In this article , an analytical model for a twin gate tunnel field effect transistor's drain current operating in the sub-threshold and superthreshold regions is proposed, the ratio of transconductance to drain current, a crucial metric for the integrated analog circuit design technique, has been retrieved.

A Fully Analytical Current Model for Gate–Source Overlap Tunneling FETs as the Ternary Devices

TL;DR: In this article , an accurate potential model of the ternary gate-source overlap tunneling FETs is presented for the face-tunnel region considering the quasi-mobile charges (QMCs).
Journal ArticleDOI

A Non-Quasi-Static Model for Nanowire Gate-All-Around Tunneling Field-Effects-Transistors

TL;DR: In this article , a non-quasi-static (NQS) device model is developed for nanowire gate-all-around (GAA) TFETs, which can predict the transient current and capacitance varied with operation frequency.
References
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Journal ArticleDOI

Tunnel field-effect transistors as energy-efficient electronic switches

TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI

Tunnel Field-Effect Transistors: State-of-the-Art

TL;DR: In this paper, the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology.
Journal ArticleDOI

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

TL;DR: In this paper, the authors have developed models allowing a direct comparison between the single-gate, double-gate and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible.
Journal ArticleDOI

Tunneling Field-Effect Transistor: Capacitance Components and Modeling

TL;DR: In this paper, a numerical simulation study of gate capacitance components in a tunneling field effect transistor (TFET) was performed, showing key differences in the partitioning of gate capacitor between the source and drain as compared with a MOSFET.
Journal ArticleDOI

A Dielectric-Modulated Tunnel-FET-Based Biosensor for Label-Free Detection: Analytical Modeling Study and Sensitivity Analysis

TL;DR: In this paper, an analytical model for a p-n-p-n tunnel field effect transistor (TFET) working as a biosensor for label-free biomolecule detection purposes is developed and verified with device simulation results.
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