Showing papers on "Bipolar junction transistor published in 2004"

Si/SiGe heterostructures: from material and physics to devices and circuits

Abstract: Silicon germanium (SiGe) has moved from being a research material to accounting for a small but significant percentage of manufactured semiconductor devices. This percentage is predicted to increase substantially as SiGe begins to be used in complementary metal oxide semiconductor (CMOS) technology in the future to substantially improve performance. It is the development of Si/SiGe heterostructures which has enabled band structure and strain engineering allowing Si/SiGe to be used in many different ways to improve conventional microelectronic device performance along with allowing new concepts to be explored. This paper presents a review of the material properties, growth techniques, band structure and the main electronic devices of the Si/SiGe heterostructure system. In particular, the important device technologies in mainstream microelectronics of the SiGe heterostructure bipolar transistor (HBT) and strained-Si CMOS will be reviewed before future device and optoelectronics concepts are explored.

Carbon nanotube p-n junction diodes

Abstract: We demonstrate a single-walled carbon nanotube p-n junction diode device. The p-n junction is formed along a single nanotube by electrostatic doping using a pair of split gate electrodes. By biasing the two gates accordingly, the device can function either as a diode or as an ambipolar field-effect transistor. The diode current–voltage characteristics show forward conduction and reverse blocking characteristics, i.e., rectification. For low bias conditions, the characteristics follow the ideal diode equation with an ideality factor close to one.

Semiconductor device and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a bipolar transistor of a self-aligned structure which has an improved current gain cut-off frequency and maximum transmission frequency, and to provide a method of manufacturing the transistor SOLUTION: The bipolar transistor in made to have a structure where a polycrystalline silicon doped with an impurity of a second conduction type is buried in an external base polycrystalline silicon in the vicinity of an emitter at a position of the lower part of the external base polycrystalline silicon adjacent to an epitaxial base layer After an insulating film of the lower part of the external base polycrystalline silicon is etched to form a recess, a polycrystalline silicon layer doped with the impurity of the second conduction type is formed, and then etched back to leave the polycrystalline silicon only in the recess, thus obtainable the bipolar transistor COPYRIGHT: (C)2005,JPO&NCIPI

Three-dimensional integrated circuit structure and method of making same

Abstract: Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate Stackable add-on layers may include interconnect lines

Semiconductor device and method of manufacturing the same

Abstract: A semiconductor device includes a p -silicon substrate, n -epitaxial growth layers on the p -silicon substrate, a field insulating film at the surface of the n -epitaxial growth layer, an npn transistor formed at the n -epitaxial growth layer, an pnp transistor formed at the n -epitaxial growth layer, a DMOS transistor on the n -epitaxial growth layer, and a resistance. The DMOS transistor includes an n -diffusion layer forming a source, a p-type diffusion layer forming a back gate region, a lightly doped n-type diffusion layer forming a drain, and a heavily doped n -diffusion layer forming the drain.

Method for making a three-dimensional integrated circuit structure

Abstract: Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and/or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.

Magnetic bipolar transistor

Abstract: A magnetic bipolar transistor is a bipolar junction transistor with one or more magnetic regions, and/or with an externally injected nonequilibrium (source) spin. It is shown that electrical spin injection through the transistor is possible in the forward active regime. It is predicted that the current amplification of the transistor can be tuned by spin.

Laser operation of a heterojunction bipolar light-emitting transistor

Abstract: Data are presented demonstrating the laser operation (quasicontinuous, ∼200K) of an InGaP–GaAs–InGaAs heterojunction bipolar light-emitting transistor with AlGaAs confining layers and an InGaAs recombination quantum well incorporated in the p-type base region Besides the usual spectral narrowing and mode development occurring at laser threshold, the transistor current gain β=ΔIc∕ΔIb in common emitter operation decreases sharply at laser threshold (65→25,β>1)

Highly Efficient Gating and Doping of Carbon Nanotubes with Polymer Electrolytes

Abstract: Carbon nanotube transistors exhibiting high on-state conductance, carrier mobilities, and on−off ratios are achieved using polymer electrolytes as gate media. Nearly ideal gate efficiencies allow operation at very small voltages without the commonly observed problem of hysteresis in back-gated nanotube and nanowire transistors. By varying the electron donating and accepting ability of the chemical groups of the host polymer, unipolar p or n devices or ambipolar transistors that are stable at room temperature in air are also shown to be easily fabricated. With simple methods such as spin casting of polymer films, high-performance polymer electrolyte-gated nanotube transistors may provide useful components for and an alternative route to developing hybrid electronics.

Ambipolar-to-Unipolar Conversion of Carbon Nanotube Transistors by Gate Structure Engineering

Abstract: The switching behavior of carbon nanotube field-effect transistors (CNFETs) can be improved by decreasing the gate oxide thickness. However, decreasing the oxide thickness also results in more pronounced ambipolar transistor characteristics and higher off-currents. To achieve high-performance unipolar CNFETs as required for CMOS logic gates, we have fabricated partially gated CNFETs with an asymmetric gate structure with respect to the source and drain electrodes. With our gate structure engineering concept, p-type CNFETs have been fabricated from an ambipolar CNFET. It is also found that fringing fields from source and drain are important in determining the CNFET behavior as the device size decreases.

Light-emitting transistor: Light emission from InGaP/GaAs heterojunction bipolar transistors

Abstract: This letter reports the direct observation of the radiative recombination in the graded base layer of InGaP/GaAs heterojunction bipolar transistors (HBTs). For a 1 μm×16 μm emitter HBT, we demonstrate the change of the spontaneous light emission intensity (ΔIout) as the base current (Δib) of the HBT is varied from 0 to 5 mA, i.e., an HBT operating as a light-emitting transistor. We also demonstrate output light modulation from the base layer at 1 MHz with the base current modulated at 1 MHz in normal transistor mode operation of the HBT.

Quantum-well-base heterojunction bipolar light-emitting transistor

Abstract: This letter reports the enhanced radiative recombination realized by incorporating InGaAs quantum wells in the base layer of light-emitting InGaP/GaAs heterojunction bipolar transistors (LETs) operating in the common-emitter configuration. Two 50 A In1−xGaxAs (x=85%) quantum wells (QWs) acting, in effect, as electron capture centers (“traps”) are imbedded in the 300 A GaAs base layer, thus improving (as a “collector” and recombination center) the light emission intensity compared to a similar LET structure without QWs in the base. Gigahertz operation of the QW LET with simultaneously amplified electrical output and an optical output with signal modulation is demonstrated.

Precision temperature measurement using CMOS substrate pnp transistors

Abstract: This paper analyzes the nonidealities of temperature sensors based on substrate pnp transistors and shows how their influence can be minimized. It focuses on temperature measurement using the difference between the base-emitter voltages of a transistor operated at two current densities. This difference is proportional to absolute temperature (PTAT). The effects of series resistance, current-gain variation, high-level injection, and the Early effect on the accuracy of this PTAT voltage are discussed. The results of measurements made on substrate pnp transistors in a standard 0.5-/spl mu/m CMOS process are presented to illustrate the effects of these nonidealities. It is shown that the modeling of the PTAT voltage can be improved by taking the temperature dependency of the effective emission coefficient into account using the reverse Early effect. With this refinement, the temperature can be extracted from the measurement data with an absolute accuracy of /spl plusmn/0.1/spl deg/C in the range of -50 to 130/spl deg/C.

High density SRAM cell with latched vertical transistors

Abstract: High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same

Abstract: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistor operative to write data in the memory transistor.

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

Abstract: The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.

A back-wafer contacted silicon-on-glass integrated bipolar process. Part II. A novel analysis of thermal breakdown

Abstract: Analytical expressions for the electrothermal parameters governing thermal instability in bipolar transistors, i.e., thermal resistance R/sub TH/, critical temperature T/sub crit/ and critical current J/sub C,crit/, are established and verified by measurements on silicon-on-glass bipolar NPNs. A minimum junction temperature increase above ambient due to selfheating that can cause thermal breakdown is identified and verified to be as low as 10-20/spl deg/C. The influence of internal and external series resistances and the thermal resistance explicitly included in the expressions for T/sub crit/ and J/sub C,crit/ becomes clear. The use of the derived expressions for determining the safe operating area of a device and for extracting the thermal resistance is demonstrated.

Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors

Abstract: A measurement system comprised of an ultra-low-distortion function generator, lock-in amplifier, and semiconductor parameter analyzer is used for sensitive extraction of the small-signal thermal impedance network of bipolar devices and circuits. The extraction procedure is demonstrated through measurements on several silicon-on-glass NPN test structures. Behavioral modeling of the mutual thermal coupling obtained by fitting a multipole rational complex function to measured data is presented.

Multiple doping level bipolar junctions transistors and method for forming

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed

Measuring cell and measuring field comprising measuring cells of this type, use of a measuring and use of a measuring field

Abstract: A measuring cell for recording an electrical potential of an analyte situated on the measuring cell. The measuring cell has a sensor, a layer arranged above the sensor and electrically insulating the analyte from the sensor, and an amplifier circuit connected to the sensor on a substrate and having an input stage containing a field-effect transistor or a bipolar transistor, the sensor being at least indirectly connected to a control terminal of the field-effect transistor or of the bipolar transistor. An operating point of the amplifier circuit is set by means of a voltage or a current applied at the control terminal of the field-effect transistor or of the bipolar transistor of the input stage of the amplifier circuit.

The super junction bipolar transistor: a new silicon power device concept for ultra low loss switching applications at medium to high voltages

Abstract: A new silicon power device concept based on the super junction (SJ) principle for power electronics in a broad spectrum of consumer, industrial and other energy conversion applications is presented in this paper. This new concept can help to sustain the trend towards ultra low loss switching––the past, present and future dominant driving force in the development of silicon high power switches. The super junction bipolar transistor (SJBT) shares many similarities with the super junction MOSFET. It has a similar MOS control structure integrated on the cathode side on top of a base region, which is organized into a columnar structure of alternating p- and n-doped pillars. The anode consists of a p-doped emitter––the SJBT is thus a bipolar super junction power device with carrier modulation taking place in only some portion of the base. The super junction structure makes up for fundamentally different device characteristics compared to an IGBT: carrier modulation in the SJBT is made possible by elimination of the reverse bias between p- and n-doped pillars when large quantities of majority carriers are injected from the p-emitter into the p-type pillar. With the electrostatic potential being grounded at the cathode, de-biasing of the pillars as well as carrier modulation will vanish towards the cathode. The unique characteristic of the SJBT on-state is an electron–hole plasma originating at the anode, which will segregate and give place to unipolar current flow in both pillars (de-mixing of the plasma) in the base region close to the cathode. Compared to an IGBT, the SJBT offers the same or lower conduction losses at a very small fraction (25%) of the cost in terms of switching losses.

Charge enhancement effect in NMOS bulk transistors induced by heavy ion Irradiation-comparison with SOI

Abstract: This work investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF-state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar-like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies.

Kink effect in short-channel polycrystalline silicon thin-film transistors

Abstract: Excess current, induced by impact ionization (kink effect) has been investigated in short-channel polysilicon thin-film transistors (TFTs). We have shown, both experimentally and by using two-dimensional (2-D) numerical simulations, that the output characteristics are substantially degraded by the kink effect as the channel length is reduced. In particular, we have shown that the excess current, triggered by the impact ionization and enhanced by the parasitic bipolar transistor action, scales nearly as L−2, thus making very difficult the downscaling of polysilicon TFTs. Such L dependence has been clarified through a detailed analysis of the current components obtained from 2-D numerical simulations. The analysis demonstrates that there are fundamental issues with the output characteristics, and it appears that the introduction of appropriate drain field relief structures will be necessary for the fabrication of short-channel polysilicon TFTs with high output impedance.

Phase change memory cell on silicon-on insulator substrate

Abstract: The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first doped region flanked by a set of second doped regions; a phase change material positioned on the first doped region; and a conductor positioned on the phase change material, wherein when the phase change material is a first phase the semiconductor structure operates as a bipolar junction transistor, and when the phase change material is a second phase the semiconductor structure operates as a field effect transistor.

Self-aligned InP DHBT with f/sub /spl tau// and f/sub max/ over 300 GHz in a new manufacturable technology

Abstract: We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.

Revised method for extraction of the thermal resistance applied to bulk and SOI SiGe HBTs

Abstract: A revision is presented of the technique to determine the junction temperature and thermal resistance of bipolar transistors. It is based on the temperature sensitivity of the base-emitter voltage when biasing the device under constant emitter current. It accounts correctly for the self-heating of the device during the measurement. Results are obtained for devices fabricated on silicon-on-insulator (SOI) and bulk silicon having different emitter widths and lengths. An increment of the thermal resistance is found for SOI devices with respect to bulk.

High-power characteristics of GaN/InGaN double heterojunction bipolar transistors

Abstract: High-power characteristics have been investigated for GaN/InGaN double heterojunction bipolar transistors (HBTs) on SiC substrates. A base-collector diode showed a high breakdown voltage exceeding 50 V, which is ascribed to a wide band gap of a GaN collector. The maximum collector current is proportional to the emitter size in the emitter-size ranging from 1.5×10−5 to 1.4×10−4 cm2. The corresponding maximum collector current density is as high as 6.7 kA/cm2, indicating the high current density characteristics of bipolar transistors. A 50 μm×30 μm device operated up to a collector–emitter voltage of 50 V and a collector current of 80 mA in its common-emitter current–voltage characteristics at room temperature. The corresponding power density is as high as 270 kW/cm2, showing that nitride HBTs are promising for high-power electronic devices in terms of both the material and the device structure.

BiCMOS technology on SOI substrates

Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer. The structure also includes an extrinsic base heterojunction bipolar transistor located in an opening provided in a bipolar device area of the SOI substrate in which a base region of the bipolar transistor is located directly atop the sub-collector

Proton tolerance of fourth-generation 350 GHz UHV/CVD SiGe HBTs

Abstract: We report, for the first time, the impact of proton irradiation on fourth-generation SiGe heterojunction bipolar transistors (HBTs) having a record peak unity gain cutoff frequency of 350 GHz. The implications of aggressive vertical scaling on the observed proton tolerance is investigated through comparisons of the pre-and post-radiation ac and dc figures-of-merit to observed results from prior SiGe HBT technology nodes irradiated under identical conditions. In addition, transistors of varying breakdown voltage are used to probe the differences in proton tolerance as a function of collector doping. Our findings indicate that SiGe HBTs continue to exhibit impressive total dose tolerance, even at unprecedented levels of vertical profile scaling and frequency response. Negligible total dose degradation in /spl beta/ (0.3%), f/sub T/ and f/sub max/(6%) are observed in the circuit bias regime, suggesting that SiGe HBT BiCMOS technology is potentially a formidable contender for high-performance space-borne applications.