Showing papers on "Gate oxide published in 2020"

Evaluation of Aging's Effect on Temperature-Sensitive Electrical Parameters in SiC mosfets

Abstract: The temperature-sensitive electrical parameters (TSEPs) have been used in silicon carbide (SiC) mosfets junction temperature measurement for over-temperature protection and condition monitoring. However, the device aging can affect the TSEPs and thus leads to false ${\boldsymbol{T}}_{\boldsymbol{j}}$ measurement. In this article, the aging's impacts on various TSEPs are comprehensively investigated. Specifically, utilizing the dc power cycling test, both the gate oxide instability and package degradation are considered. Then the commercial devices with different structures are aged, and their temperature-dependent static and switching characteristics are evaluated at different aging cycles. Both the positive gate bias-induced threshold voltage shift and package degradation are observed, and their impacts on each TSEP are evaluated independently. Based on the evaluation results at various operating conditions, the temperature measurement errors due to different aging mechanisms are well summarized for each TSEP. From the dc power cycling test result, the package degradation's impact on TSEPs is found to be more significant than the gate oxide instability. It is pointed out that the aging's effect on TSEPs is an important factor that needs to be considered for accurate ${\boldsymbol{T}}_{\boldsymbol{j}}$ measurement in SiC mosfets .

High Speed Memory Operation in Channel-Last, Back-gated Ferroelectric Transistors

Abstract: Scaled ferroelectric transistors (L g =76 nm) in a back- gated configuration are fabricated with a channel-last process flow. Using this approach, optimization of the ferroelectric gate oxide film can be decoupled from that of the semiconductor channel to reduce parasitic interfaces. As a result, ferroelectric transistors with 3σ memory window for fast programming time of 10 ns (including an instantaneous read-after-write) at 1.8 V and high endurance of 1012 cycles are demonstrated for the first time.

Radiation-hardened and repairable integrated circuits based on carbon nanotube transistors with ion gel gates

Abstract: Electronics devices that operate in outer space and nuclear reactors require radiation-hardened transistors. However, high-energy radiation can damage the channel, gate oxide and substrate of a field-effect transistor (FET), and redesigning all vulnerable parts to make them more resistant to total ionizing dose irradiation has proved challenging. Here, we report a radiation-hardened FET that uses semiconducting carbon nanotubes as the channel material, an ion gel as the gate and polyimide as the substrate. The FETs exhibit a radiation tolerance of up to 15 Mrad at a dose rate of 66.7 rad s−1, which is notably higher than the tolerance of silicon-based transistors (1 Mrad). The devices can also be used to make complementary metal–oxide–semiconductor (CMOS)-like inverters with similarly high tolerances. Furthermore, we show that radiation-damaged FETs can be recovered by annealing at a moderate temperature of 100 °C for 10 min. By using carbon nanotubes as a channel material, an ion gel as a gate and polyimide as a substrate, field-effect transistors can be created that have a high radiation tolerance and can be repaired by annealing.

Design and Performance Analysis of Tunnel Field Effect Transistor With Buried Strained Si 1− x Ge x Source Structure Based Biosensor for Sensitivity Enhancement

Abstract: In this paper, a dielectrically modulated symmetrical double gate, having dual gate material, Tunnel Field-Effect transistor with Buried strained Si1- x Ge x source structure, has been investigated as a biosensor. This structure is proposed for the very first time to electrically detect the biological molecules at very low power consumption. In the proposed biosensor structure, the top thin Si channel of TFET is overlapped with the Si1- x Ge x source. This increases the tunneling area, due to which ON current of the biosensor also increases. To detect the biomolecules a nanogap cavity has been created over 1nm gate oxide. Also to decrease the short channel effects, dual-gate material with different metal work functions is used on both the symmetrical double gates. By varying the small bandgap material (Ge) mole fraction in the SiGe and after inserting different biological molecules (of the different dielectric) in a cavity, the variation in transfer characteristic, $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ current ratio, SS along with their sensitivity is studied. Also, to signify the presence of biomolecules in the cavity, the $\text{g}_{m}/\text{I}_{d}$ ratio as a sensing metric is studied under the sub-threshold region. Along with the fully filled biomolecules cavity, the partially filled cavity and the effect of a steric hindrance have also investigated in this paper with various non-uniform step patterns of biomolecules in the cavity. Because, in a more practical situation, the steric hindrance effect doesn’t allow the cavity to be entirely filled. Also, this paper addresses the optimization of drain current sensitivity, by different cavity length with different source overlapping cavity.

Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application

Abstract: We have fabricated and demonstrated ultrathin In-Ga-Zn-O (IGZO) channel ferroelectric HfO 2 field effect transistor (FET) with memory operation. Ultrathin-body IGZO ferroelectric FET (FeFET) shows high mobility and nearly ideal subthreshold slop with minimum 8 nm channel thickness, thanks to the properties of IGZO material, junctionless FET operation, nearly-zero low-k interfacial layer on metal-oxide channel and effective capping for realizing ferroelectric phase formation with HfZrO 2 (HZO). The controllable memory operations are achieved with the use of back gate. The design guideline of IGZO FeFET is proposed by discussing the thickness of front gate oxide HZO and back gate oxide SiO 2 using TCAD simulation. The material and electrical properties of metal/HZO/IGZO/metal capacitor are also investigated. Metal/HZO/IGZO/metal capacitor has up to 10 8 endurance and over one-year retention. IGZO FeFET shows a potential for high-density and low-power memory application.

Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

Abstract: This paper investigates the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator. For this, we have observed the effects of different ITCs on both conventional dual material control gate tunnel field effect transistor (DMCG-TFET) and dual-material gate-oxide-stack double-gate TFET with identical dimensions in terms of DC, analog/RF and linearity performance parameters. Both the devices with positive (donor) and negative (acceptor) ITCs, have been simulated using technology computer-aided design (TCAD) tool. To understand the impact of different ITCs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance, parasitic capacitance, $f_{T}$ , GBP and TFP for DMGOSDG-TFET have been analyzed and compared with that of DMCG-TFET. Further, to analyze the effect of different ITCs on the linearity performances, the parameters VIP2, VIP3, IIP3 and IMD3 have been investigated and compared with that of the conventional DMCG-TFET. Simulation results demonstrate that DMGOSDG-TFET is more immune towards different types of ITCs as compared to the conventional DMCG-TFET. Hence, DMGOSDG-TFET is more reliable over the conventional device for ultra low power applications.

Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body Diode

Abstract: Eliminating antiparallel silicon carbide Schottky barrier diode (SiC SBD) and making use of the intrinsic body diode of SiC metal–oxide–semiconductor-field-effect transistor (SiC MOSFET) offer a cost-effectiveness solution without obviously sacrificing the conversion efficiency in some power converter applications. Although the body diode of commercial SiC MOSFET has been qualified by several manufacturers, the reliability of SiC MOSFET under repetitive surge current stress of body diode has not been sufficiently studied. In this article, the new degradation phenomena of SiC MOSFET’s gate oxide are observed, and the degradation mechanism is discussed when the intrinsic body diode of the 1200-V SiC planar gate MOSFETs was subjected to surge current stress. TCAD simulation and experimental measurements indicate that the generation and accumulation of electrons or holes within the gate oxide under surge current stress are the main reasons for the degradation of SiC MOSFET. Finally, a mitigation technique with optimal gate turn-off voltage is suggested to suppress the gate oxide degradation of the SiC MOSFET under surge current stress of its body diode.

Ionizing-Radiation Response and Low-Frequency Noise of 28-nm MOSFETs at Ultrahigh Doses

Abstract: Total ionizing dose (TID) mechanisms are investigated in 28-nm MOSFETs via dc static and low-frequency noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on the channel length, the channel width, and the bias condition. Halo implantations improve the radiation tolerance of shorter-channel transistors. Worst case bias for TID-induced degradation is found with high electric field applied to the gate during irradiation, due to increased charge trapping in the upper corner of the shallow trench isolation (STI) and in the gate oxide. DC and low-frequency noise measurements show that, at doses up to ~100 Mrad(SiO2), radiation-induced degradation is primarily due to the positive charge buildup in the STI oxides. At ultrahigh doses approaching 1 Grad(SiO2), TID degradation is influenced by charge buildup in the gate oxide and traps at or near the gate/dielectric interface and/or along the STI sidewalls. Worst case degradation is found in narrower and longer-channel devices, due to the enhanced charge buildup in the STI oxide and along its interfaces.

Effect of Gate-Oxide Degradation on Electrical Parameters of Silicon Carbide MOSFETs

Abstract: Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been identified as precursors (indicators) for monitoring the gate-oxide degradation process in Si MOSFETs, very few have been identified for their SiC counterparts. The purpose of this article is twofold. The first objective is to demonstrate that the three gate-oxide degradation precursors identified for Si MOSFETs: 1) threshold voltage, 2) gate-plateau voltage, and 3) gate-plateau time can also be extended to SiC MOSFETs. The second objective is to demonstrate analytically and experimentally that all three precursors increase in a linear-with-log-stress-time manner during gate-oxide degradation in both planar and trench-gate SiC MOSFETs. The increasing trends of precursors and their associated logarithmic time responses were experimentally verified by inducing accelerated gate-oxide degradation in two different commercial SiC MOSFETs (650-V, 70-A trench-gate MOSFETs and 1200-V, 19-A planar MOSFETs) under high temperatures of 150 and 125 °C, respectively.

Total-Ionizing-Dose Effects and Low-Frequency Noise in 16-nm InGaAs FinFETs With HfO 2 /Al 2 O 3 Dielectrics

Abstract: Total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO2/Al2O3 gate-stack. Transistors are irradiated up to 500 krad(SiO2) and annealed at high temperatures. Irradiated devices show negative threshold-voltage Vth shifts, subthreshold stretch-out, and leakage current increases. These result from positive charge trapping in the gate oxide and shallow trench insulators, and increases in the interface and border-trap charge densities. Low-frequency noise measurements at different temperatures indicate a significant increase of noise magnitude in irradiated devices at an activation energy of ~0.4 eV. Density functional theory (DFT) calculations strongly suggest that transistor Vth shifts are due primarily to hole trapping at oxygen vacancies in HfO2, and the increased noise is due primarily to O vacancies in Al2O3. Additional contributions to the noise from defects in the GaAs buffer layer are also likely, primarily at low temperatures.

A Charge-to-Breakdown (Q BD ) Approach to SiC Gate Oxide Lifetime Extraction and Modeling

Abstract: This paper proposes a charge-to-breakdown (Q BD ) approach for SiC/SiO 2 dielectric lifetime extraction. The current through the dielectric is shown to be a combination of Fowler Nordheim (FN) and thermally assisted tunneling (TAT). The former leads to positive charge trapping, the latter to negative charge storage in border traps near the SiC/SiO 2 interface. Both degradation mechanisms have a distinctly different failure distribution function. Time-to-fail extracted from constant field TDDB (standard industry technique) is unable to capture the effects of these different charge trapping mechanisms on the failure distribution function, in contrast to constant current Q BD stress. Hence, time-to-fail from Q BD stress leads to a more accurate and physics based lifetime prediction.

Sensitive field-effect transistor sensors with atomically thin black phosphorus nanosheets

Abstract: Atomically thin black phosphorus (BP) field-effect transistors have excellent potential for sensing applications. However, commercial scaling of PFET sensors is still in the early stage due to various technical challenges, such as tedious fabrication, low response% caused by rapid oxidation, non-ideal response output (spike/bidirectional), and large device variation due to poor control over layer thickness among devices. Attempts have been made to address these issues. First, a theoretical model for response% dependence on the number of layers is developed to show the role of atomically thin BP for better responses. A position-tracked, selected-area-exfoliation method has been developed to rapidly produce thin BP layers with a narrow distribution (∼1–7 layers), which can harness excellent gate control over the PFET channel. The typical current on/off ratio is in the range of ∼300–500. The cysteine-modified Al2O3-gated PFET sensors show high responses (∼30–900%) toward a wide detection range (∼1–400 ppb) of lead ions in water with a typical response time of ∼10–30 s. A strategy to minimize device variation is proposed by correlating PFETs’ on/off ratio with sensitivity parameters. The thickness variation of the gate oxide is investigated to explain non-ideal and ideal response transient kinetics.

Gate-oxide reliability and failure-rate reduction of industrial SiC MOSFETs

Abstract: We discuss various gate-oxide reliability aspects of silicon carbide (SiC) MOSFETs and highlight similarities and differences of SiC and silicon (Si) technology. Basic concepts of electrical gate-oxide defect screening are introduced and failure probability and the failure-rate after screening is studied based on Weibull statistics. To be able to quantify very low extrinsic failure probabilities (e.g. after electrical screening), we present a new kind of test procedure which we call the "marathon stress test". The results of this test demonstrate that excellent gate-oxide reliability of commercially available SiC trench MOSFETs can be achieved after applying a sufficiently precise electrical screening.

Thin film transistors based on ultra-wide bandgap spinel ZnGa2O4

Abstract: We report on thin film transistors (TFTs) based on spinel ZnGa2O4 (ZGO) that was recently spotlighted as an ultra-wide bandgap oxide semiconductor. The ZGO layers were grown in a spinel structure by pulsed laser deposition on the cubic spinel MgAl2O4 (MAO) as well as on cubic MgO substrates while changing the Zn/Ga ratio. The compressive strained epitaxial growth of ZGO on MgAl2O4 (100) and the tensile strained epitaxial growth of ZGO on MgO (100) without any misfit or threading dislocations were confirmed by the reciprocal space map and cross-sectional transmission electron microscopy. The electrical transport properties were demonstrated through TFTs based on ZGO as the channel layer, Al2O3 as the gate oxide, and Sn-doped In2O3 as the source, drain, and gate electrodes. When the Zn/Ga ratio is slightly lower than the ideal value of 0.5 on MgO substrates, the ZGO TFT showed the highest mobility of 5.4 cm2/V s. The ION/IOFF ratio and subthreshold swing (S) value are 4.5 × 108 and 0.19 V/dec, respectively.

Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor

Abstract: We present a two-dimensional (2-D) analytical modeling of the surface potential of a double-gate vertical t-shaped tunnel field-effect transistor (TFET), considering the inherit dual modulation effect in such devices. This effect explains the control of the surface potential by both bias voltages, which are used to calculate the tunneling depletion width at the source and drain junctions. A model of the tunneling current in the device is derived based on the surface-potential model. The parabolic approximation is used to solve the 2-D Poisson equation with appropriate boundary conditions. The dependence of the surface potential profile on different parameters is analyzed by varying the gate–source potential, drain–source potential, gate oxide dielectric constant, gate metal work function, and different materials used. Finally, expressions for the surface potential of the channel along with the tunneling current are obtained, accurately capturing their variation with the gate and drain biases. The proposed method is verified by the agreement between its analytical results and technology computer-aided design (TCAD) simulation results.

Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis

Abstract: Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimizing the performances of metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper, near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated combining transient gate capacitance measurements (C-t) and state of the art scanning transmission electron microscopy in electron energy loss spectroscopy (STEM-EELS) with sub-nm resolution. The C-t measurements as a function of temperature indicated that the effective NIOTs discharge time is temperature independent and electrons from NIOTs are emitted toward the semiconductor via-tunnelling. The NIOTs discharge time was modelled taking into account also the interface state density in a tunnelling relaxation model and it allowed to locate traps within a tunnelling distance up to 1.3nm from the SiO2/4H-SiC interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence of a Non-Abrupt (NA) SiO2/4H-SiC interface. The NA interface shows the re-arrangement of the carbon atoms in a sub-stoichiometric SiOx matrix. A mixed sp2/sp3 carbon hybridization in the NA interface region suggests that the interfacial carbon atoms have lost their tetrahedral SiC coordination.

Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

Abstract: This paper investigates the trap analysis of a double-gate extended-source tunnel field-effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor (SG-ESTFET) with a δp+ SiGe pocket layer. The trap analysis of both structures is compared in terms of the currents, average subthreshold swing, threshold voltage, and switching ratio. In addition, the impact of interface trap charges at different interfaces on analog/RF performance, transfer characteristics, and slope are investigated and compared. It is observed that the trap charges between the silicon and front gate oxide interface (Si–HfO2) have a greater effect on the DG-ESTFET than the SG-ESTFET, whereas the reverse is true when trap charges are at the back gate oxide interface (Si–SiO2). In the case of analog/RF performance, the SG-ESTFET is found to be more affected by the trap charges at the silicon and front gate oxide interface (Si–HfO2).

The Effects of Valence Band Offset on Threshold Voltage Shift in a-InGaZnO TFTs Under Negative Bias Illumination Stress

Abstract: In this paper, we propose a novel mechanism for the $\text{V}_{{\text {th}}}$ shift of amorphous-indium gallium zinc oxide (a-IGZO) thin film transistors under negative bias illumination stress (NBIS). Three kinds of IGZO TFTs with different gate dielectrics and valence band offsets (VBO) were used in this experiment. Gate dielectric materials used were Al2O3, HfO2 and SiO2. Initial parameters, VBO, and state density (DOS) for each TFT were extracted. After NBIS, the $\text{V}_{\text {th}}$ shift was greatest at −3.82 V using a TFT with an HfO2 gate dielectric. VBO was the lowest at 0.38 eV using a TFT with an HfO2 gate dielectric. The smaller the VBO, the larger the generated $\text{V}_{\text {th}}$ shift. DOS measurements confirmed the interfacial properties between the gate dielectric and IGZO, and the highest DOS resulted from the interface between Al2O3 and IGZO. Through the experimental results, the correlation between VBO and $\Delta \text{V}_{{\text {th}}}$ after NBIS was investigated. We found that the main cause of $\text{V}_{{\text {th}}}$ shift in NBIS is injection of photoinduced hole carriers that cross the VBO by tunneling from IGZO channel to gate oxide.

4H-SiC CMOS Transimpedance Amplifier of Gamma-Irradiation Resistance Over 1 MGy

Abstract: A transimpedance amplifier (TIA)—with gamma-irradiation resistance of over 1 MGy—based on a novel 4H-SiC complementary MOS (CMOS) technology was fabricated. This TIA is robust enough to be applied in measuring instruments installed in nuclear power plants or other harshly irradiated environments. The SiC CMOS transistors comprising the TIA feature a thin (8-nm-thick) gate oxide to reduce the threshold-voltage shift ( ${V}_{{\text {th}}}$ ) due to irradiation by more than 90% compared with that of the conventional transistors. Oxynitride protection formed at the SiC–SiO2 interface in the thin gate-oxide region suppresses the deterioration of mobility by interface traps generated by the gamma radiation. The TIA consisting of these SiC-CMOS transistors operated properly up to at least 1.2 MGy without an increase in the offset voltage, although its open-loop gain was degraded due to deteriorated mobility of the p-channel metal–oxide–semiconductor field-effect transistor (MOSFET). On the other hand, increasing the drain leakage current in the nonactive region impeded further improvement of the SiC TIA under a high integral dose. To decrease the drain leakage current, a structure with a high doping concentration layer between the source and the drain in the nonactive region was fabricated. The structure stops the parasitic transistor turning on and the trap-assisted current increasing. The leakage current of the improved structure is about 42% lower than that of a conventional structure.

Comparative Study of Variations in Gate Oxide Material of a Novel Underlap DG MOS-HEMT for Analog/RF and High Power Applications

Abstract: In this paper an Underlap Double Gate (U-DG) Symmetric Heterojunction AlGaN/GaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) with gate oxide materials of different dielectric constant has been studied using gate oxide materials such as Hafnium dioxide (HfO2), Silicon dioxide (SiO2) and a symmetric gate stack (GS) of HfO2-SiO2. In this work, the analog performance of the devices has been studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/ID) and intrinsic gain (gmR0). This paper depicts the effect of varying oxide materials on the analog and RF figure of merits (FOMs) such as the gate to drain capacitance (CGD), gate to source capacitance (CGS) and total gate capacitance (CGG), intrinsic resistances, cut-off frequency (fT) and maximum frequency of oscillation (fMAX) using non-quasi-static approach. Studies show that the introduction of a gate oxide layer in the MOS-HEMT device increases the gate controllability reducing gate leakage currents improving RF performance. U-DG AlGaN/GaN MOS-HEMT with HfO2 gate dielectric shows superior Power output efficiency (POE) of 55% compared to the HfO2-SiO2 composite structure and SiO2 with 26% and 20% respectively.

On-Current Enhancement in TreeFET by Combining Vertically Stacked Nanosheets and Interbridges

Abstract: The TreeFET channel, which is a combination of vertically stacked nanosheet channels and fin-shaped interbridge channels in between the nanosheets, can provide an additional channel conduction area to improve the on-current without increasing the device footprint. To provide on-current enhancement, a minimum height is required for the interbridge that is dependent on the width of the interbridge and the physical gate oxide thickness. Minimizing the threshold voltage difference between the interbridges and the nanosheet channels also plays a crucial role in the optimization of the on-current of TreeFETs. The design criteria for TreeFETs are studied using TCAD simulation of Ge nFETs.

Cryogenic characterization of a ferroelectric field-effect-transistor

Abstract: A ferroelectric field-effect transistor (FeFET) with scaled dimensions (170 nm and 24 nm of gate width and length, respectively) and a 10 nm thick Si doped HfO 2 ferroelectric in the gate oxide stack are characterized at cryogenic temperatures down to 6.9 K. We observe that a decrease in temperature leads to an increase in the memory window at the expense of an increased program/erase voltage. This is consistent with the increase in the ferroelectric coercive field due to the suppression of thermally activated domain wall creep motion at cryogenic temperatures. However, the observed insensitivity of the location of the memory window with respect to temperature cannot be explained by the current understanding of the device physics of FeFETs. Such temperature dependent studies of scaled FeFETs can lead to useful insights into their underlying device physics, while providing an assessment of the potential of this emerging technology for cryogenic memory applications.

Highly reliable AlSiO gate oxides formed through post-deposition annealing for GaN-based MOS devices

Abstract: The electrical stabilities of AlSiO gate oxides formed through post-deposition annealing (PDA) and intended for GaN-based power devices were assessed. No degradation of the interface properties of AlSiO/n-type GaN or the oxide breakdown voltage was observed, even after PDA up to 1050 °C. Furthermore, higher temperature PDA drastically reduced the trap density in the oxide, as indicated by current–voltage and positive bias temperature instability data. Time-to-breakdown characteristics showed sufficient lifetimes above 20 years at 150 °C in an equivalent field of 5 MV cm−1. Therefore, AlSiO films fabricated by high-temperature PDA are reliable gate oxide films for GaN-based devices.

Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis

Abstract: The effects of stacked SiO2/HfO2 gate oxide, source pocket, and underlap gate engineering on the electrical and RF performances of cylindrical gate tunnel field-effect transistors (CGTFETs) have been investigated in this paper. While source pocket with underlap engineering reduces both the gate leakage current and subthreshold swing (SS), the stacked gate oxide improves the drain current of the CGTFET. The DC and RF performance parameters such as the electric field, drain current, transconductance, gate capacitance, unity gain cut-off frequency, gain–bandwidth product, transconductance frequency product, and intrinsic delay have been investigated for different stacked oxide CGTFETs with and without a source pocket as well as with and without an underlap structure. Our study demonstrates that the proposed underlapped stacked-oxide source-pocket engineered CGTFET structure not only enhances the drain current, but also improves the subthreshold switching characteristics of the device by reducing SS and gate leakage current.

Fabrication process and failure analysis for robust quantum dots in silicon.

Abstract: We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topology beneath them, independent of gate geometry and identify critical dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.

Comparison of Hafnium Dioxide and Zirconium Dioxide Grown by Plasma-Enhanced Atomic Layer Deposition for the Application of Electronic Materials

Abstract: We report the growth of nanoscale hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) thin films using remote plasma-enhanced atomic layer deposition (PE-ALD), and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using the HfO2 and ZrO2 thin films as the gate oxide. Tetrakis (dimethylamino) hafnium (Hf[N(CH3)2]4) and tetrakis (dimethylamino) zirconium (IV) (Zr[N(CH3)2]4) were used as the precursors, while O2 gas was used as the reactive gas. The PE-ALD-grown HfO2 and ZrO2 thin films were analyzed using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and high-resolution transmission electron microscopy (HRTEM). The XPS measurements show that the ZrO2 film has the atomic concentrations of 34% Zr, 2% C, and 64% O while the HfO2 film has the atomic concentrations of 29% Hf, 11% C, and 60% O. The HRTEM and XRD measurements show both HfO2 and ZrO2 films have polycrystalline structures. n-channel and p-channel metal-oxide semiconductor field-effect transistors (nFETs and pFETs), CMOS inverters, and CMOS ring oscillators were fabricated to test the quality of the HfO2 and ZrO2 thin films as the gate oxide. Current-voltage (IV) curves, transfer characteristics, and oscillation waveforms were measured from the fabricated transistors, inverters, and oscillators, respectively. The experimental results measured from the HfO2 and ZrO2 thin films were compared.

Optimization of Electrical Parameters of Pocket Doped SOI TFET with L Shaped Gate

Abstract: In this work, a pocket doped hetero source Silicon-on-insulator Tunneling Field Effect Transistor (SOI-TFET) with L shaped gate including back gate is proposed. The operation of this device is primarily dependent on band to band tunneling. Performance of a p-i-n TFET (proposed structure 1) is examined against the SOI double gate TFET (proposed structure 2). A brief investigation of the proposed device has been done by drain bias variation, EOT scaling, channel length modulation, pocket thickness variation, substrate dimension scaling and back gate voltage variation using Sentaurus TCAD software. The device performance is optimized for different source, drain, channel and pocket doping concentration and work function tuning of the front gate. It provides a high Ion/Ioff ratio, best reported 3.326 × 1011; steep Subthreshold Swing, SS best reported point SS 22.21 mV/decade (2 nm gate oxide) and average SS 31.74 mV/decade (3 nm gate oxide). The ON current is found to be high i.e. in the orders of mA. The proposed device is immune to short channel effects like DIBL and channel length modulation.

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress.

Abstract: The origin of dielectric breakdown was studied on 4H-SiC MOSFETs that failed after three months of high temperature reverse bias stress. A local inspection of the failed devices demonstrated the presence of a threading dislocation (TD) at the breakdown location. The nanoscale origin of the dielectric breakdown was highlighted with advanced high-spatial-resolution scanning probe microscopy (SPM) techniques. In particular, SPM revealed the conductive nature of the TD and a local increase of the minority carrier concentration close to the defect. Numerical simulations estimated a hole concentration 13 orders of magnitude larger than in the ideal 4H-SiC crystal. The hole injection in specific regions of the device explained the failure of the gate oxide under stress. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.