Showing papers on "Power semiconductor device published in 2020"

A 1.86-kV double-layered NiO/β-Ga2O3 vertical p–n heterojunction diode

Abstract: In this Letter, high-performance vertical NiO/β-Ga2O3 p–n heterojunction diodes without any electric field managements were reported. The devices show a low leakage current density and a high rectification ratio over 1010 (at ±3 V) even operated at temperature of 400 K, indicating their excellent thermal stability and operation capability at high temperature. Given a type-II band alignment of NiO/β-Ga2O3, carrier transport is dominated by the interface recombination at forward bias, while the defect-mediated variable range hopping conduction is identified upon strong reverse electric field. By using the double-layer design of NiO with a reduced hole concentration of 5.1 × 1017 cm−3, the diode demonstrates an improved breakdown voltage (Vb) of 1.86 kV and a specific on-resistance (Ron,sp) of 10.6 mΩ cm2, whose power figure of merit (Vb2/Ron,sp) has reached 0.33 GW/cm2. The high breakdown voltage and low leakage current are outperforming other reported Ga2O3 based p–n heterojunctions and Schottky barrier diodes without field plate and edge termination structures. TCAD simulation indicates that the improved Vb is mainly attributed to the suppression of electric field crowding due to the decreased hole concentration in NiO. Such bipolar heterojunction is expected to be an alternative to increase the breakdown characteristics of β-Ga2O3 power devices.

A Review on Reduced Switch Count Multilevel Inverter Topologies

Abstract: Multilevel Inverters (MLIs) are becoming more and more popular in medium and high power applications. This is due to several inherent advantages of MLI over two-level inverters such as high-quality output, lower device ratings, and several others. While the classical topologies are still having applications in most of the key areas, there is a growing interest in newer multilevel topologies with an objective of reducing power semiconductor device count, gate drivers and/or isolated DC sources. In this paper, a comprehensive review of some of the recently proposed newer multilevel inverter topologies with the abovementioned objectives is presented. In this article, a detailed investigation in terms of total power semiconductor switch count, number of DC sources, passive component requirement, highest switch voltage rating, total standing voltage etc. has been presented.

Overview of Real-Time Lifetime Prediction and Extension for SiC Power Converters

Abstract: Remaining useful lifetime prediction and extension of Si power devices have been studied extensively. Silicon carbide (SiC) power devices have been developed and commercialized. Specifically, SiC mosfet s have been utilized for the next generation high-voltage, high-power converters with smaller size and higher efficiency, covering various mainstream applications, including photovoltaic systems, electric vehicles, solid-state transformers, and more electric ships and airplanes. However, the SiC-based devices have different failure modes and mechanisms compared with Si counterparts. Therefore, a comprehensive review is critical to develop accurate lifetime prediction and extension strategies for SiC power converter systems. The SiC power device component-level failure modes and mechanisms are first investigated. Different accelerated lifetime tests and component-level lifetime models are then compared. Power converter system-level offline lifetime modeling techniques and software tools are further summarized. Besides, the SiC power converter condition monitoring strategies and health indicators are surveyed. The online measurement challenges are also studied. Furthermore, the system-level lifetime extension strategies are reviewed. By integrating device physics, statistical modeling, reliability engineering, and mechanical engineering with power electronics, this article is intended to provide a comprehensive overview, address existing challenges, and unfold new research opportunities regarding the SiC power converter real-time lifetime prediction and extension.

GaN Power Integration for High Frequency and High Efficiency Power Applications: A Review

Abstract: High frequency and high efficiency operation is one of the premier interests in the signal and energy conversion applications. The wide bandgap GaN based devices possess superior properties and have demonstrated exceeding performance than Si or GaAs devices. In order to further exploit the potential of GaN electronics, monolithic power integration is proposed. Firstly, this paper discusses the structure and properties of GaN power devices to explain the choice of lateral integration in the view of GaN power ICs. Then the state-of-the-art performance of GaN power integration in two major application areas is reviewed, which are the microwave power amplification and DC-DC power conversion. The GaN power integration technologies in MMIC platforms are summarized in terms of the gate length, operation frequency and power added efficiency of ICs. On the other hand, the smart GaN power IC platforms have boosted the development of DC-DC power converters. Demonstrations of high frequency (>1 MHz) and high efficiency (>95 %) converters with various kinds of integration technology and topology are reviewed. Lastly novel integration schemes and methods are introduced to stimulate new thoughts on GaN power integration road.

Surge-Energy and Overvoltage Ruggedness of P-Gate GaN HEMTs

Abstract: An essential ruggedness of power devices is the capability of safely withstanding the surge energy. The surge ruggedness of the GaN high-electron-mobility transistor (HEMT), a power transistor with no or minimal avalanche capability, has not been fully understood. This article unveils the comprehensive physics associated with the surge-energy withstand process and the failure mechanisms of p-gate GaN HEMTs. Two commercial p-gate GaN HEMTs with Ohmic- and Schottky-type gate contacts are studied. Two circuits are developed to study the device surge ruggedness: an unclamped inductive switching circuit is first used to identify the withstand dynamics and failure mechanisms, and a clamped inductive switching circuit with a controllable parasitic inductance is then designed to mimic the surge energy in converter-like switching events. The p-gate GaN HEMT is found to withstand the surge energy through a resonant energy transfer between the device capacitance and the load/parasitic inductance rather than a resistive energy dissipation as occurred in the avalanche. If the device resonant voltage goes below zero, the device reversely turns on and the inductor is discharged. The device failure occurs at the transient of peak resonant voltage and is limited by the device overvoltage capability rather than the surge energy, dV/dt , or overvoltage duration. Almost no energy is dissipated in the resonant withstand process and the device failure is dominated by an electric field rather than a thermal runaway. These results provide critical understandings on the ruggedness of GaN HEMTs and important references for their qualifications and applications.

Adaptive Multi-Level Active Gate Drivers for SiC Power Devices

Abstract: State-of-the-art silicon carbide (SiC) power devices provide superior performance over silicon devices with much higher switching frequencies/speed and lower losses. High switching speed is preferred for achieving low switching loss, yet high dv/dt and di/dt can result in high EMI emission during switching transients. These switching dynamics can be controlled by the device gate driving strategy. The multi-level active gate driver (AGD) approach is able to tradeoff the switching losses with the dv/dt and di/dt for each switching transient. A novel three-level (3-L) AGD for SiC power mosfet trajectory control is introduced. Its turn-off profile has a shorter turn-off delay compared to any existing methodology. Accordingly, a comprehensive datasheet-driven trajectory model for the online model-based optimization of the 3-L turn-off is introduced. The main factors that impact the 3-L turn-off performance are analyzed with this model. The experimental results of double pulse tests validate the approach. Additionally, the benefits of the proposed 3-L AGD method over two-stage turn-off and conventional gate drivers on the market are illustrated through experiments.

10-kV SiC MOSFET Power Module With Reduced Common-Mode Noise and Electric Field

Abstract: The advancement of silicon carbide (SiC) power devices with voltage ratings exceeding 10 kV is expected to revolutionize medium- and high-voltage systems. However, present power module packages are limiting the performance of these unique switches. The objective of this research is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The high-speed switching and high voltage rating of these devices causes significant EMI and high electric fields. Existing power module packages are unable to address these challenges, resulting in detrimental EMI and partial discharge that limit the converter operation. This article presents the design and testing of a 10-kV SiC mosfet power module that switches at a record 250 V/ns without compromising the signal and ground integrity due to an integrated screen reduces the common-mode current by ten times. This screen connection simultaneously increases the partial discharge inception voltage by more than 50%. With the integrated cooling system, the power module prototype achieves a power density of 4 W/mm3.

(Ultra)Wide-Bandgap Vertical Power FinFETs

Abstract: FinFET is the backbone device technology for CMOS electronics at deeply scaled technology nodes per Moore’s law. Recently, the FinFET concept has been leveraged to develop a new generation of vertical power transistors based on wide-bandgap (WBG) and ultrawide-bandgap (UWBG) semiconductors for kilovolts and high-power applications. The sidewall gate-stack in a vertical power FinFET can rely on either a metal–oxide–semiconductor (MOS) structure or a p-n junction, rendering a Fin-MOSFET or a fin-based junction field-effect transistor (Fin-JFET), respectively. Although the device technologies are still at the early stage of development, 1.2-kV-class WBG gallium nitride (GaN) power Fin-MOSFETs have demonstrated one of the highest static and switching performances in all similarly rated power transistors; UWBG gallium oxide power Fin-MOSFETs have shown high performance up to a breakdown voltage over 2.6 kV. Early UWBG diamond lateral power Fin-MOSFETs have also been demonstrated. Meanwhile, GaN power Fin-JFETs are currently under active development. This article provides a comprehensive tutorial and review of the background and recent advances in WBG and UWBG vertical power FinFETs. It covers fundamental device physics, device and process development, as well as the static and switching performance of various power Fin-MOSFETs and Fin-JFETs. This article is concluded by identifying the current challenges and exciting research opportunities in this very dynamic research field.

A Survey on Switching Oscillations in Power Converters

Abstract: High-frequency power converters enabled by wide bandgap (WBG) and silicon semiconductor devices offer distinct advantages in power density and dynamic performance. However, switching oscillations are commonly observed in these circuits with undesirable consequences. This paper reviews the impacts, root causes, and mitigation techniques of switching oscillations through literature survey, modeling analysis, and experimental investigation. We categorize the following root causes for oscillations during switching transients: 1) damped oscillation triggered by high di/dt and/or dv/dt coupled with parasitic elements; 2) undamped oscillation of WBG devices as part of a negative resistance oscillator; and 3) semiconductor device physical mechanisms such as the negative capacitance phenomenon due to conductivity modulation in insulated gate bipolar transistors or impact ionization in MOSFETs, the plasma extraction transit-time effect in bipolar power devices, and the reverse conduction property of GaN HEMTs. Furthermore, this paper discusses various circuit techniques to suppress switching oscillations, and techniques of extracting parasitic inductances of power devices.

An Ultra-High Step-Up DC–DC Converter With Extendable Voltage Gain and Soft-Switching Capability

Abstract: In this article, a new high step-up dc–dc converter with soft-switching capability is presented. In this converter, all of the main and the auxiliary power switches operate under soft-switching condition. In addition, the leakage inductances of the coupled inductors control the current falling rate of the power diodes. Therefore, the reverse recovery losses are reduced significantly. In addition, the voltage stresses across the power semiconductors and clamped capacitors are limited to lower values. In this converter, coupled inductors and diode-capacitor voltage multiplier (VM) cells are utilized simultaneously to provide higher voltage gain. This combination increases the flexibility of the proposed converter, because the turn ratios of the coupled inductors and the number of VM cells are the degrees of freedom which can be used to regulate the voltage stress across the semiconductors. In this article, detailed analysis, elements design, and comparison results are presented. Furthermore, in order to validate the theoretical analysis, a 500-W, 19–60-V/400-V laboratory prototype of the proposed converter is built, and the related results are investigate.

1.2 kV Vertical GaN Fin JFETs with Robust Avalanche and Fast Switching Capabilities

Abstract: This work, for the first time, demonstrates a 1.2-kV-class, 4-A normally-off vertical GaN fin-channel JFET on GaN substrate, and characterizes its static and dynamic performance as well as avalanche robustness. The device shows an on/off current ratio of ~109, a specific on-resistance (R ON ) of 0.82 mΩ·cm2, and a threshold voltage (V TH ) over 0.5 V extracted at a drain current of 1 mA. The on/off ratio and V TH exhibit very little changes at high temperatures up to 125°C. A robust avalanche is observed under the unclamped inductive switching (UIS) conditions, showing an avalanche breakdown voltage (BV AVA ) of 1470 V and an avalanche current (I AVA ) over 1 A. The I AVA is found to mainly flow through the p-GaN gate instead of the n-GaN fins. The JFET also shows small junction capacitances. Double-pulse tests at 600-V/4-A reveal a rise/fall time of 12.9 ns/10.3 ns and a total loss of 37 μJ. Almost no reverse recovery is observed on the body diode, due to the short lifetime of minority carriers. To the best of our knowledge, we report one of the highest Baliga’s figure-of-merit (BV2/R ON ) and the first avalanche robustness in vertical GaN power transistors. Our results suggest the great potential of vertical GaN JFETs for medium-voltage high-frequency power applications.

Strain-controlled power devices as inspired by human reflex.

Abstract: Bioinspired electronics are rapidly promoting advances in artificial intelligence. Emerging AI applications, e.g., autopilot and robotics, increasingly spur the development of power devices with new forms. Here, we present a strain-controlled power device that can directly modulate the output power responses to external strain at a rapid speed, as inspired by human reflex. By using the cantilever-structured AlGaN/AlN/GaN-based high electron mobility transistor, the device can control significant output power modulation (2.30–2.72 × 103 W cm−2) with weak mechanical stimuli (0–16 mN) at a gate bias of 1 V. We further demonstrate the acceleration-feedback-controlled power application, and prove that the output power can be effectively adjusted at real-time in response to acceleration changes, i.e., ▵P of 72.78–132.89 W cm−2 at an acceleration of 1–5 G at a supply voltage of 15 V. Looking forward, the device will have great significance in a wide range of AI applications, including autopilot, robotics, and human-machine interfaces. Designing intelligent power devices that can directly control the output power modulation responses to external stimuli at a rapid speed remains a challenge. Here, the authors report a strain-controlled power device by using the cantilever-structured AlGaN/AlN/GaN HEMT to emulate human reflex process.

High-Density Current-Transformer-Based Gate-Drive Power Supply With Reinforced Isolation for 10-kV SiC MOSFET Modules

Abstract: With features such as faster switching frequency and higher breakdown voltage, wide bandgap power devices are key enablers to address the increasing demand for higher power density and higher efficiency in future medium-voltage converters. The 10-kV SiC MOSFET is one of such devices; yet, to fully utilize its benefits, a gate-drive power supply capable of meeting the necessary insulation (voltage) and isolation ( dv/dt voltage slew rate) requirements is needed. To this end, this article presents the complete design and optimization of such a power supply meeting four critical objectives: 1) high power density with high-voltage (HV) insulation; 2) minimum input–output capacitance; 3) fault ride-through capability; and 4) good voltage regulation. To this end, a GaN-based inductor-capacitor-capacitor-inductor (LCCL)- LC resonant converter switching at 1 MHz was used to produce a resonant current source and to supply multiple isolated loads (gate-drivers) through the single-turn primary winding loop. Experimental results are shown demonstrating the attained power density (6.3 W/in3), input–output capacitance (1.67 pF), peak efficiency (86.0%), short- and open-circuit fault withstanding capacity, and insulation rating (partial discharge inception voltage of 12 kV).

Accurate Temperature Estimation of SiC Power mosfet s Under Extreme Operating Conditions

Abstract: Electrothermal modeling of silicon carbide (SiC) power devices is frequently performed to estimate the device temperature in operation, typically assuming a constant thermal conductivity and/or heat capacity of the SiC material. Whether and by how much the accuracy of the resulting device temperature prediction under these assumptions is compromised has not been investigated so far. Focusing on high-temperature operating conditions as found under short circuit (SC), this paper presents a comprehensive analysis of thermal material properties determining the temperature distribution inside SiC power mosfet s. Using a calibrated technology computer-aided design (TCAD) electrothermal model, it is demonstrated that the temperature prediction of SiC power devices under SC operation when neglecting either the top metallization or the temperature dependence of the heat capacity is inaccurate by as high as 25%. The presented analysis enables to optimize compact electrothermal models in terms of accuracy and computational time, which can be used to assess the maximum temperature of SiC power mosfet s in both discrete packages and multichip power modules exposed to fast thermal transients. A one-dimensional thermal network of a SiC power mosfet is proposed based on the thermal material properties, the size of the active area of the device, and its thickness.

New Figure-of-Merit Combining Semiconductor and Multi-Level Converter Properties

Abstract: Figures-of-Merit (FOMs) are widely-used to compare power semiconductor materials and devices and to motivate research and development of new technology nodes. These material- and device-specific FOMs, however, fail to directly translate into quantifiable performance in a specific power electronics application. Here, we combine device performance with specific bridge-leg topologies to propose the extended FOM, or X-FOM, a Figure-of-Merit that quantifies bridge-leg performance in multi-level (ML) topologies and supports the quantitative comparison and optimization of topologies and power devices. To arrive at the proposed X-FOM, we revisit the fundamental scaling laws of the on-state resistance and output capacitance of power semiconductors to first propose a revised device-level semiconductor Figure-of-Merit (D-FOM). The D-FOM is then generalized to a multi-level topology with an arbitrary number of levels, output power, and input voltage, resulting in the X-FOM that quantitatively compares hard-switched semiconductor stage losses and filter stage requirements across different bridge-leg structures and numbers of levels, identifies the maximum achievable efficiency of the semiconductor stage, and determines the loss-optimal combination of semiconductor die area and switching frequency. To validate the new X-FOM and showcase its utility, we perform a case study on candidate bridge-leg structures for a three-phase 10 kW photovoltaic (PV) inverter, with the X-FOM showing that (a) the minimum hard-switching losses are an accurate approximation to predict the theoretically maximum achievable efficiency and relative performance between bridge-legs and (b) the 3-level bridge-leg outperforms the 2-level configuration, despite utilizing a SiC MOSFET with a lower D-FOM than in the 2-level case.

An Intelligent Versatile Model-Based Trajectory-Optimized Active Gate Driver for Silicon Carbide Devices

Abstract: Using silicon carbide (SiC) power devices can potentially improve the efficiency of a power electronic system, but it may also introduce severe electromagnetic interference (EMI) problems due to the fast switching speed. The conventional gate driver cannot provide the flexibility to adjust the switching speed of SiC dynamically. To address this issue, an intelligent versatile active gate driver (AGD) is proposed to achieve optimized switching trajectory for power devices. The proposed AGD has five operation modes, i.e., faster/normal/slower the turn-on process and slower/normal turn-off process. The availability of multiple operation modes offers extra freedom to improve the switching performance and enable it to be versatile across various systems. The proposed AGD can provide more switching speed adjustment resolution than the other AGDs allowing for fine tuning of the switching speed of SiC power devices. In addition, a novel model-based trajectory optimization strategy is proposed to determine the optimal gate driver output voltage by trading the EMI noise against the switching energy losses. The functionalities of the multi-level AGD are validated with the experimental results. The hardware design consideration is also given for the product commercialization purpose.

Demonstration of 1200 V/1.4 mΩ cm2 vertical GaN planar MOSFET fabricated by an all ion implantation process

Abstract: We present a vertical GaN planar MOSFET fabricated by an all ion implantation process. The fabricated MOSFET shows an on-resistance of 2.78 mΩ cm2 and a breakdown voltage of 1200 V, by applying the short cell pitch design to reduce the on-resistance and a Mg and N sequential implantation to improve the breakdown voltage of the pn-junction. By evaluating each on-resistance component in the fabricated vertical GaN planar MOSFET using the simultaneously formed test structures, an effective on-resistance of the active region excluding the source parasitic resistance is 1.4 mΩ cm2. Consequently, it was demonstrated that an all ion implantation process can fabricate a vertical GaN planar MOSFET with a high breakdown voltage and low on-resistance. This result will greatly contribute to the realization of GaN power devices.

Commercial GaN-Based Power Electronic Systems: A Review

Abstract: Wide bandgap semiconductor technology is gaining widespread acceptance in the area of high-power and high-temperature power electronics. Gallium nitride (GaN) not only has a wide bandgap of 3.4 eV and all the associated superior electronic properties but also enables the development of high-mobility power devices which is critical in increasing the power density of a power electronics system. Since a commercial GaN power transistor has a lateral structure as opposed to the traditional vertical device structure, commercially available devices are rated below 1000 V breakdown voltage with a maximum value of 900 V and typical value around 650 V. The primary focus of this review will be to introduce readers to the commercially available power electronic systems developed by various manufacturers which employ GaN-based power devices and highlight their remarkable performance which surpasses existing technology. This review also includes a brief introduction on GaN technology followed by current market study showing the roadmap of integration of GaN-based power electronics in the power industry.

Design and Experimental Validation of a Wire-Bond-Less 10-kV SiC MOSFET Power Module

Abstract: Wide bandgap (WBG) power devices with voltage ratings exceeding 10 kV have the potential to revolutionize medium- and high-voltage systems due to their high-speed switching and lower ON-state losses. However, the present power module packages are limiting the performance of these unique switches. The objective of this article is to push the boundaries of high-density, high-speed, 10-kV power module packaging. The proposed package addresses the well-known electromagnetic and thermal challenges, as well as the more recent and prominent electrostatic and electromagnetic interference (EMI) issues associated with high-speed, 10-kV devices. The module achieves low and balanced parasitic inductances, resulting in a record switching speed of 250 V/ns with negligible ringing and voltage overshoot. An integrated screen reduces the common-mode (CM) current that is generated by these fast voltage transients by ten times. This screen connection simultaneously increases the partial discharge inception voltage (PDIV) by more than 50%. A compact, medium-voltage termination and system interface design is also proposed in this article. With the integrated jet-impingement cooler, the power module prototype achieves a power density of 4 W/mm3. This article presents the design, prototyping, and testing of this optimized package for 10-kV SiC MOSFETs.

Experimental Characterization of Silicon and Gallium Nitride 200 V Power Semiconductors for Modular/Multi-Level Converters Using Advanced Measurement Techniques

Abstract: The increasing demand for higher power densities and higher efficiencies in power electronics, driven by the aerospace, electric vehicle, and renewable energy industries, encourages the development of new converter concepts. In particular, modular and/or multi-level (M/ML) topologies are employed to break the performance barriers of the state-of-the-art power converters by simultaneously reducing the system losses and volume/weight. These improvements mainly originate from the replacement of high-voltage transistors, typical of two-level converters, with low-voltage, e.g., 200 V, devices, offering superior electric performance. Hence, two low on-state resistance silicon (Si) and gallium nitride (GaN) 200 V power semiconductors are comprehensively characterized in this article to support the multi-objective optimization and the design of M/ML power converters. First, the selected devices are analyzed experimentally determining their conduction, thermal, and switching characteristics; for this purpose, a novel ultra-fast transient calorimetric measurement method is introduced and explained in detail. In the course of this analysis, an unexpected switching loss mechanism is observed in the Si devices at hand; the physical reason of this behavior is clarified and it is proven to be solved in the next-generation research samples, which are also characterized by measurements. Finally, the influence of the measured power semiconductors’ performance on the overall efficiency and power density of a typical converter is determined through a case study analyzing a hard switching half-bridge operated as a single-phase inverter, i.e., the fundamental building block of several M/ML topologies. It is concluded that, in this voltage and power class, GaN e-FETs are nowadays approximately a factor of three superior to Si power MOSFETs; however, the better heat dissipation achieved by the latter still makes them the preferred solution for higher power applications.

Fundamental research on semiconductor SiC and its applications to power electronics

Abstract: Today, the silicon carbide (SiC) semiconductor is becoming the front runner in advanced power electronic devices. This material has been considered to be useful for abrasive powder, refractory bricks as well as ceramic varistors. Big changes have occurred owing to the author’s inspirational idea in 1968 to “make transistors from unusual material”. The current paper starts by describing the history of SiC research involving fundamental studies by the author’s group: unique epitaxial crystal growth techniques, the physical characterization of grown layers and processes for device fabrication. Trials for fabricating SiC power devices and their characteristics conducted until 2004 are precisely described. Recent progress in SiC crystal growth and peripheral techniques for SiC power devices are introduced. Finally, the present progress concerning SiC power devices is introduced together with the implementation of those devices in society.

Planar GaN Power Integration – The World is Flat

Abstract: GaN power IC’s are expected to help unlock the full potential of GaN power electronics, especially in terms of promoting the high-frequency power switching applications. This paper first discusses a GaN power integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated gate driver is presented as an example of GaN power IC with enhanced performance, in which a bootstrap unit is adopted to realize rail-to-rail output voltage and fast switching speed. To deal with GaN-specific design issues such as the unique dynamic V TH , a SPICE model of p-GaN gate HEMT is developed to improve design accuracy. Future prospects for GaN power integration are discussed by extending the integration’s landscape to multi-functional GaN power devices, GaN CMOS technology, and GaN/SiC hybrid power IC’s.

An Active Voltage Balancing Control Based on Adjusting Driving Signal Time Delay for Series-Connected SiC MOSFETs

Abstract: Limited by low availability, high price, and poor switching performance of high-voltage power devices, connecting low-voltage devices in series to block much higher voltages is always an option. However, severe voltage unbalance during turn-off transient remains to be solved. Most of the existing methods designed for low-speed silicon (Si) insulated gate bipolar transistor (IGBT) cannot be directly transplanted to the series-connected silicon carbide (SiC) MOSFETs with high switching speed. To maximum the switching performance of SiC MOSFETs, an elegant implementation of adjusting driving signal time delay method is proposed. In addition, a simplified model during drain–source voltage rising transient is discussed to basically reveal features and problems of the series-connected SiC MOSFETs. The factors affecting the appropriate time delay are discussed as well, especially the influence of the load current. The simplified model and the implementation are both verified by experiments. Indeed, the proposed active voltage balancing control works well and has no penalty of sacrificing switching performance of SiC MOSFETs.

Design and fabrication of field-plated normally off β-Ga2O3 MOSFET with laminated-ferroelectric charge storage gate for high power application

Abstract: In this work, an enhancement-mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) has been achieved by incorporating a laminated-ferroelectric charge storage gate (L-FeG) structure [Al2O3/HfO2/Al2O3/Hf05Zr05O2 (HZO) of 10/5/2/16 nm] The band diagram between L-FeG dielectrics (Al2O3, HfO2, and HZO) and β-Ga2O3 was determined by x-ray photoelectron spectroscopy After applying a gate pulse with an intensity of +18 V and width of 1 ms, the saturation current of the E-mode device was measured to be 232 mA/mm, which shows a negligible current reduction compared to that of 221 mA/mm in a depletion- (D-) mode device In addition, the threshold voltage (VTH) is only shifted by 276% and 218%, respectively, after applying the gate stress and gate-drain stress of 15 V for 104 s Meanwhile, a high breakdown voltage of 2142 V and specific on-resistance (RON,sp) of 2384 mΩ·cm2 were also achieved, which correspond to a state-of-art high power figure of merit of 1925 MW/cm2, showing the great potential of combing the ferroelectric gate stack and lateral Ga2O3 MOSFET as next generation power devices

Three-Phase Bidirectional Buck-Boost Current DC-Link EV Battery Charger Featuring a Wide Output Voltage Range of 200 to 1000V

Abstract: High power EV chargers connected to an AC power distribution bus are employing a three-phase AC/DC Power Factor Correction (PFC) front-end and a series-connected isolated DC/DC converter to efficiently regulate the traction battery voltage and supply the required charging current. In this paper, the component stresses and the design optimization of a novel two-stage three-phase bidirectional buck-boost current DC-link PFC rectifier system, realized solely with SiC power MOSFETs and conveniently requiring only a single magnetic component, are introduced. This topology offers a high efficiency in a wide operating range thanks to the synergetic operation of its two stages, the three-phase buck-type current source rectifier stage and the subsequent three-level boost-type DC/DC-stage, which makes it suitable for on-board as well as off-board charger applications. The calculated voltage and current component stresses of the proposed converter system, considering an output voltage range of 200 to 1000V and up to 10kW of output power, help to identify its operating boundaries, maximizing the utilization of the power semiconductors and of the DC-link inductor. The optimum values of the circuit parameters are selected after evaluating the converter average efficiency $\bar \eta $ and volumetric power density ρ in the Pareto performance space and analyzing its design space diversity, focusing on the semiconductor losses and on the characteristics of the inductor. Considering typical EV battery charging profiles, i.e. taking both full-load and part-load operation into account, a power converter realization featuring $\bar \eta = 98.5\% $ and ρ =13.9kW/dm3 is achieved.

Cascode GaN/SiC: A Wide-Bandgap Heterogenous Power Device for High-Frequency Applications

Abstract: Wireless power transfer systems and plasma generators are among the increasing number of applications that use high-frequency power converters. Increasing switching frequency can reduce the energy storage requirements of the passive elements that can lead to higher power densities or even the elimination of magnetic cores. However, operating at higher frequencies requires faster switching devices in packages with low parasitics. Wide-bandgap (WBG) power devices, such as gallium nitride (GaN) and silicon carbide (SiC) devices, have high-critical fields and high-thermal conductivity that make them good candidates for efficient high-voltage and high-frequency operations. Commercially available GaN and SiC devices have ratings targeting different applications. Lateral GaN devices dominate in lower voltage ( $C_{\text{oss}},C_{\text{iss}}$ ), which make them easy to drive at high frequencies. On the other hand, vertical SiC devices are often used in high-voltage and low-frequency applications since they have higher blocking voltages and larger gate charge than their GaN counterparts. As a result, SiC devices usually require high power and complicated gate drive circuitry. Recent work shows that in both GaN and SiC devices, losses in device $C_{\text{oss}}$ can exceed the conduction losses at high-switching frequencies and relatively high voltages under zero-voltage-switching conditions. Moreover, the $C_{\text{oss}}$ energy loss ( $E_{\text{oss}}$ ) per switching cycle increases with frequency in GaN devices but remains roughly independent of frequency in SiC devices. This means that at high frequencies, SiC devices can be preferable due to their smaller $C_{\text{oss}}$ energy loss even when taking into consideration the complexity of the gate drive circuit. In this article, we present a WBG high-voltage cascode GaN/SiC power device, combining the advantages of both a GaN and an SiC device—namely, simple gate drive requirements, $E_{\text{oss}}$ loss per cycle roughly independent of frequency, and relatively high-voltage blocking capability. Comparing this cascode GaN/SiC device with an SiC mosfet and a SiC junction gate field-effect transistor of similar voltage ratings and $R_{ds,{\text{ON}}}$ , we find that the inverter using the cascode GaN/SiC device has the highest efficiency and simplest auxiliary gate drive circuitry. Finally, integrating the cascode GaN/SiC device has the potential benefits of achieving lower $C_{\text{oss}}$ losses, higher device ratings, and better heat removal capability.

Two-Phase, Dual Interleaved Buck–Boost DC–DC Converter for Automotive Applications

Abstract: A two-phase buck–boost converter utilizing dual interleaving is presented in this article. The dual interleaving consists of an interphase transformer (IPT) that doubles the ripple frequency together with two conventional buck–boost switching arms, mitigating the inductor ripple current and aiding to increase the power density of the converter. A description of the design and selection of the power devices is presented for a 32-kW, 75-kHz dual interleaved SiC prototype with an IPT, such that a power density of 7.4 kW/kg is achieved. The operation of the circuit is verified experimentally using a prototype with 315–385 V supply range and 350-V output voltage, achieving 97.1% peak efficiency at 32 kW. The experiments reveal that the interleaved coupled currents are equalized without an active balancer.

11.1 A Direct 12V/24V-to-1V 3W 91.2%-Efficiency Tri-State DSD Power Converter with Online V CF Rebalancing and In-Situ Precharge Rate Regulation

Abstract: In industrial and automotive applications, 12V/24V power systems are widely used. In such systems, high step-down DC-DC converter is highly desirable to deliver a wide range of current directly to the point of load for high power density and efficiency [1]. In this scenario, the conventional half-bridge topology faces severe challenges of extremely short on-time and highly unbalanced power losses between high-side and low-side switches. On the other hand, switched-capacitor (SC) topologies exhibit obvious drawbacks on insufficient current handling and discrete conversion ratios (CRs). Recently, Hybrid topologies have been presented to use SC topology at the front-end to lower the high V IN voltage stress across power devices, and then use inductive topology at the back-end for current delivery. Accordingly, the inductor size can be greatly reduced to improve system density and low voltage rating devices are used for high efficiency and fast switching. Among hybrid topologies, 3-level [2] and double step-down (DSD) topologies [3] are popular examples, as shown in Fig. 11.1.1. However, 3-level topology uses two low-side switches to discharge inductor, largely increasing conduction loss for high input voltage (V IN ) and CR. On the other hand, increasing V IN imposes high voltage stress on switch S H2 in DSD topology, compromising the reliability. At high switching frequency, very short on-times in both topologies make gate drive and feedback loop design highly challenging at high CRs.

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks

Abstract: The breakdown performance is a critical metric for power device design. This paper explores the feasibility of efficiently predicting the breakdown performance of silicon on insulator (SOI) lateral power device using multi-layer neural networks as an alternative to expensive technology computer-aided design (TCAD) simulation. In this work, we propose the first breakdown performance prediction framework, PowerNet, for SOI lateral power devices, based on deep learning methods. The framework can provide breakdown location prediction and breakdown voltage (BV) prediction by utilizing a two-stage machine learning method. In addition, it demonstrates 97.67% accuracy on breakdown location prediction and less than 4% average error on the BV prediction compared with TCAD simulation. The proposed method can be used to measure changes in performance caused by random variability in structural parameters during manufacturing process, allowing designers to avoid unstable structural parameters and enhance design robustness. More importantly, it can significantly reduce the computational cost when compared with the TCAD simulation. We believe the proposed machine learning technique can significantly speedup the design space exploration for power devices, eventually reducing the overall product-to-market time.