Rao Tummala

TL;DR: In this paper, the authors focus on the reliability of TPVs in polycrystalline silicon interposers fabricated from panels, and they show lower stresses in TPVs with thick polymer liners, compared with TSVs in traditional single-crystaline silicon with thin SiO2 layers.

TL;DR: In this paper, a two-metal layer RDL structure at 40 um pitch on thin glass interposers is proposed to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices.

TL;DR: In this article, in-situ warpage and stress measurements were made to analyze the observed failure modes and to set guidelines for optimal board material selection, and the effect of interlayer dielectric thickness on the package reliability has also been studied.

TL;DR: In this article, a substrate-compatible panel-level process was developed to embed the magnetic-core inductors with high throughput and low cost, which achieved four times improvement in inductance for the same dc resistance.

TL;DR: In this paper, a chip-last embedded active has been proposed to address some of the issues that are reported in current chip-first and -middle approaches, in which chips are embedded after all the package substrate processes including the build-up layers are completed, just like conventional SMD packaging.