R
Rao Tummala
Researcher at Georgia Institute of Technology
Publications - 628
Citations - 12781
Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.
Papers
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Proceedings ArticleDOI
Demonstration of 3–5 μm RDL line lithography on panel-based glass interposers
TL;DR: In this article, a double-sided glass interposer with 3-5 μm line lithography was used to form multilayer redistribution layers (RDL) to achieve 20 micron bump pitch, ready for chiplevel copper interconnections.
Proceedings ArticleDOI
Miniaturized High-Performance Filters for 5G Small-Cell Applications
Muhammad Ali,Fuhan Liu,Atom Watanabe,P. Markondeya Raj,Venkatesh Sundaram,Manos M. Tentzeris,Rao Tummala +6 more
TL;DR: In this paper, the first panel-based ultra-miniaturized filters with footprint smaller than half of the free-space wavelength at the operating frequencies of 28 and 39 GHz bands for 5G and mm-wave small-cell applications were demonstrated.
Journal ArticleDOI
Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost
Brett Sawyer,Yuya Suzuki,Ryuta Furuya,Chandrasekharan Nair,Ting-Chia Huang,Vanessa Smet,Kadappan Panayappan,Venky Sundaram,Rao Tummala +8 more
TL;DR: In this article, a 2.5D glass interposer is proposed to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers.
Journal ArticleDOI
Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors
Prathap Muthana,K. Srinivasan,A.E. Engin,Madhavan Swaminathan,Rao Tummala,V. Sundaram,B. Wiedenman,Daniel I. Amey,Karl Hartmann Dietz,Sounak Banerji +9 more
TL;DR: In this article, the performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in the context of simultaneous switching noise suppression.
Patent
Chip-last embedded interconnect structures and methods of making the same
TL;DR: In this paper, the chip-last embedded structure, wherein an IC is embedded within a one-to-two metal layer substrate, is described. But the chip I/O can be re-distributed to BGA or land grid arrays.