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Rao Tummala

Researcher at Georgia Institute of Technology

Publications -  628
Citations -  12781

Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.

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Journal ArticleDOI

Integral passives for next generation of electronic packaging: application of epoxy/ceramic nanocomposites as integral capacitors

TL;DR: Material and process issues for passive elements such as resistors, capacitors, and inductors and the need for developing alternative substrate materials have been addressed in this paper.
Proceedings ArticleDOI

Through-package-via formation and metallization of glass interposers

TL;DR: In this article, a glass interposer was proposed as a superior alternative interposers technology to address the limitations of both silicon and organic interposition technology, where the inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposERS.
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Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

TL;DR: In this paper, an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects is presented, which is correlated with measurement results for validation.
Proceedings ArticleDOI

A novel integrated decoupling capacitor for MCM-L technology

TL;DR: In this paper, the design, materials, fabrication and measurements of a novel integrated decoupling capacitor for MCM-L-based substrates are discussed, with diameters of 100 um and below, through photodefinable processes.
Journal ArticleDOI

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

TL;DR: A double-sided and ultrathin 3D glass interposer with through package vias at same pitch as through silicon vias in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs as discussed by the authors.