R
Rao Tummala
Researcher at Georgia Institute of Technology
Publications - 628
Citations - 12781
Rao Tummala is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Interposer & Capacitor. The author has an hindex of 43, co-authored 623 publications receiving 11663 citations. Previous affiliations of Rao Tummala include Qualcomm & IBM.
Papers
More filters
Journal ArticleDOI
Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate
TL;DR: In this paper, a sub-10 micron copper line technology was used for flip chip attaching and ultra fine copper line routing substrates were demonstrated for flip-chip attaching by using semi-additive metallization process.
Proceedings ArticleDOI
Integrated Copper Heat Spreaders in Glass Panel Embedded Packages with Near-Zero Thermal Interface Resistance
Nithin Nedumthakady,Bartlet H. DeProspo,P. Markondeya Raj,Venky Sundaram,Rao Tummala,Kyle Byers,Sean Garrison,Chris Gibson,Michael Elsbury +8 more
TL;DR: In this article, the thermal dissipation requirements of 30W-100W power amplifiers were addressed by embedding the IC in the glass substrate and direct metallization with large copper heat spreaders.
Journal ArticleDOI
Wetting of glass-to-metal and glass-to-ceramic in water-vapour atmospheres
Rao Tummala,B. J. Foster +1 more
Journal ArticleDOI
Thermal Aging Reliability of Socketable BGA Packages With Ni–Au-Coated SAC305 Spheres
TL;DR: In this article, the applicability of socketable BGA packages in socketing was evaluated by subjecting the packages to thermal aging at a temperature of 120 °C. The change in microstructure with thermal aging along with the consumption of the barrier layer was understood.
Proceedings ArticleDOI
Design and demonstration of large 2.5D glass interposer for high bandwidth applications
Taiji Sakai,Brett Sawyer,Hao Lu,Yutaka Takagi,Ryuta Furuya,Yuya Suzuki,Makoto Kobayashi,Vanessa Smet,Venky Sundaram,Rao Tummala +9 more
TL;DR: In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect, 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM).