Showing papers by "Freescale Semiconductor published in 2008"

Prognostic and Warning System for Power-Electronic Modules in Electric, Hybrid Electric, and Fuel-Cell Vehicles

Abstract: Reliability of power-electronic modules is of paramount importance for the commercial success of various types of electric vehicles. In this paper, we study the technical feasibility of detecting and utilizing early symptoms and warning signs of power-module degradation due to thermomechanical stress and fatigue and develop a prognostic system that can monitor the state of health of the power modules in electric, hybrid, and fuel-cell vehicles. A special degradation trace on the VCEsat of the insulated-gate bipolar-transistor modules was observed by a power-cycling accelerated test, which was not reported in literatures. A prognostic system based on utilizing the aforementioned trace is then developed. The system consists of the hardware architecture and current adaptive-algorithm-based software architecture. In addition, this prognostic system hardly increases the hardware cost on existing vehicle-driver system. An extensive simulation based on MATLAB/Simulink verifies the developed prognostic system.

Improved conductivity and mechanism of carrier transport in zinc oxide with embedded silver layer

Abstract: The effects of an embedded silver layer on the electrical and optical properties of zinc oxide (ZnO)/silver (Ag)/zinc oxide (ZnO) layered composite structures on polymer substrates have been investigated. We have engineered transparent conducting oxide structures with greatly improved conductivity. Optical and electrical properties are correlated with Ag thickness. Film thicknesses were determined using Rutherford backscattering spectrometry. Hall effect, four-point probe, and UV-Vis spectrophotometer analyses were used to characterize electrical and optical properties. The results show that carrier concentration, mobility, and conductivity increase with Ag thickness. Increasing Ag thickness from 8to14nm enhances sheet resistance and resistivity by six orders of magnitude. The optical transmittance of the composite structure decreases when compared to a single ZnO layer of comparable thickness. However, a composite with 12nm of Ag provides conductivity and transmittance values that are acceptable for opto...

Optimal Downlink OFDMA Resource Allocation with Linear Complexity to Maximize Ergodic Rates

Abstract: OFDMA resource allocation assigns subcarriers and power, and possibly data rates, to each user. Previous research efforts to optimize OFDMA resource allocation with respect to communication performance have focused on formulations considering only instantaneous per-symbol rate maximization, and on solutions using suboptimal heuristic algorithms. This paper intends to fill gaps in the literature through two key contributions. First, we formulate continuous and discrete ergodic weighted sum rate maximization in OFDMA assuming the availability of perfect channel state information (CSI). Our formulations exploit time, frequency, and multi-user diversity, while enforcing various notions of fairness through weighting factors for each user. Second, we derive algorithms based on a dual optimization framework that solve the OFDMA ergodic rate maximization problem with O(MK) complexity per OFDMA symbol for M users and K subcarriers, while achieving data rates shown to be at least 99.9999% of the optimal rate in simulations based on realistic parameters. Hence, this paper attempts to demonstrate that OFDMA resource allocation problems are not computationally prohibitive to solve optimally, even when considering ergodic rates.

Smart/active RFID tag for use in a WPAN

Abstract: A system and method is provided for processing communication signals in a wireless personal area network (WPAN) using a transceiver comprising a first transmitter and a first receiver operable to transmit and receive signals using a first transmission protocol and a second transmitter operable to transmit signals using a second transmission protocol. In various embodiments, the first receiver is used to receive a first signal that was transmitted using the first communication protocol and the second transmitter is used to transmit a second signal using the second transmission protocol in response to receipt of the first signal. The second signal is then processed to determine the location of the object. In some embodiments, the first transmission protocol is compliant with an Institute of Electrical and Electronics Engineers 802.15.4 transmission protocol and the second transmission protocol is compliant with an Ultra-Wide Band (UWB) protocol.

Electromagnetic shield formation for integrated circuit die package

Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

A Monolithic CMOS-MEMS 3-Axis Accelerometer With a Low-Noise, Low-Power Dual-Chopper Amplifier

Abstract: This paper reports a monolithically integrated CMOS-MEMS three-axis capacitive accelerometer with a single proof mass. An improved DRIE post-CMOS MEMS process has been developed, which provides robust single-crystal silicon (SCS) structures in all three axes and greatly reduces undercut of comb fingers. The sensing electrodes are also composed of the thick SCS layer, resulting in high resolution and large sensing capacitance. Due to the high wiring flexibility provided by the fabrication process, fully differential capacitive sensing and common-centroid configurations are realized in all three axes. A low-noise, low- power dual-chopper amplifier is designed for each axis, which consumes only 1 mW power. With 44.5 dB on-chip amplification, the measured sensitivities of x-, y-, and z-axis accelerometers are 520 mV/g, 460 mV/g, and 320 mV/g, respectively, which can be tuned by simply changing the amplitude of the modulation signal. Accordingly, the overall noise floors of the x-, y-, and z-axis are 12 mug/radicHz , 14 mug/radicHz, and 110 mug/radicHz, respectively, when tested at around 200 Hz.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

Abstract: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Frequency and Power Correlation between At-Speed Scan and Functional Tests

Abstract: At-speed scan is a key technique in modern IC testing. One of its drawbacks, with respect to functional tests, is its excessive power consumption leading to voltage drop and frequency degradation. This paper discusses the frequency and power correlation between At-speed scan and functional tests. The influence of voltage drop on frequency is demonstrated by silicon measurements and supporting simulation results. The localized nature of the voltage drop as well as impedance component analysis are presented. Additionally, the need for power aware scan patterns is also discussed. Suggestions for achieving a higher correlation between At-speed scan and functional patterns, with respect to power consumption, are offered.

Wireless communication unit, integrated circuit and method of power control of a power amplifier therefor

Abstract: A wireless communication unit comprises a transmitter having a forward path comprising a power amplifier, PA, and a feedback path arranged to feed back a portion of a signal output from the PA to a point in the forward path prior to the PA. The forward path and feedback path form a constant gain tracking (CGT) loop. The feedback path comprises an adaptive predistortion logic module located outside of the CGT loop and arranged to form an APD loop with the forward path and feedback path. The CGT loop comprises a controller logic module arranged to determine a gain offset of a signal routed through the forward path and feedback path and in response thereto set a drive level of the PA.

Modeling the Electromagnetic Emission of a Microcontroller Using a Single Model

Abstract: This paper presents a methodology for building an integrated circuit behavioral model that enables the prediction of its electromagnetic (EM) emissions up to several gigahertz. The model, built upon S-parameter characterization and conducted emission measurements, is used to predict the EM emissions of a commercial 16-bit microcontroller. The emission measurements are performed according to several EM compatibility standards, namely, 1 Omega /150 Omega , surface scan, and transverse EM/gigahertz transverse EM (GTEM) method, and their results show an excellent fit with model predictions.

Resource allocation in a communication system

Abstract: Methods and corresponding systems for determining a transmit power in a mobile device include receiving, in the mobile device, a cell-wide power control parameter related to a target receive power at a serving base station. Thereafter, a transmit power is calculated in response to the cell-wide power control parameter and an implicit mobile-specific power control parameter. The mobile device then transmits using the transmit power. The cell-wide power control parameter can be a cell target signal to interference-plus-noise ratio, or a fractional power control exponent. The implicit mobile-specific power control parameter can be a modulation and coding level previously used by the mobile device, or a downlink SINR level measured by the mobile device.

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Abstract: The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects

Stress–Strain Characteristics of Tin-Based Solder Alloys for Drop-Impact Modeling

Abstract: The stress–strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 s−1 and 300 s−1 are required to support finite-element modeling of the solder joints during board-level mechanical shock and product-level drop-impact testing. However, there is very limited data in this range because this is beyond the limit of conventional mechanical testing and below the limit of the split Hopkinson pressure bar test method. In this paper, a specialized drop-weight test was developed and, together with a conventional mechanical tester, the true stress–strain properties of four solder alloys (63Sn-37Pb, Sn-1.0Ag-0.1Cu, Sn-3.5Ag, and Sn-3.0Ag-0.5Cu) were generated for strain rates in the range from 0.005 s−1 to 300 s−1. The sensitivity of the solders was found to be independent of strain level but to increase with increased strain rate. The Sn-3.5Ag and the Sn-3.0Ag-0.5Cu solders exhibited not only higher flow stress at relatively low strain rate but, compared to Sn-37Pb, both also exhibited higher rate sensitivity that contributes to the weakness of these two lead-free solder joints when subjected to drop impact loading.

Nonuniform Sampling of Periodic Bandlimited Signals

Abstract: Digital processing techniques are based on representing a continuous-time signal by a discrete set of samples. This paper treats the problem of reconstructing a periodic bandlimited signal from a finite number of its nonuniform samples. In practical applications, only a finite number of values are given. Extending the samples periodically across the boundaries, and assuming that the underlying continuous time signal is bandlimited, provides a simple way to deal with reconstruction from finitely many samples. Two algorithms for reconstructing a periodic bandlimited signal from an even and an odd number of nonuniform samples are developed. In the first, the reconstruction functions constitute a basis while in the second, they form a frame so that there are more samples than needed for perfect reconstruction. The advantages and disadvantages of each method are analyzed. Specifically, it is shown that the first algorithm provides consistent reconstruction of the signal while the second is shown to be more stable in noisy environments. Next, we use the theory of finite dimensional frames to characterize the stability of our algorithms. We then consider two special distributions of sampling points: uniform and recurrent nonuniform, and show that for these cases, the reconstruction formulas as well as the stability analysis are simplified significantly. The advantage of our methods over conventional approaches is demonstrated by numerical experiments.

Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

Abstract: Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell, at Vd = 0.6 V, a static noise margin (SNM) of 95 mV was obtained and stable read/write operations were verified from N-curve measurements. sigmaVt of transistors in 0.187 m2 cells was measured with and without channel doping and the result was summarized in the Pelgrom plot. With the 22 nm node design rule, FinFET SRAM cell layouts were compared against planar-FET SRAM cell layouts. An un-doped FinFET SRAM cell was simulated to have significant advantage in read/write margin over a planar-FET SRAM cell, which would have higher sigmaVt mainly caused by heavy doping into the channel region.

32nm general purpose bulk CMOS technology for high performance applications at low voltage

Abstract: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.

A 77 GHz SiGe mixer in an embedded wafer level BGA package

Abstract: We present a fully operational 77 GHz SiGe mixer assembled in a chip-scale embedded wafer level BGA (eWLB) package. This innovative package has a footprint with a standard pad pitch of 0.5 mm and a standard package height of 0.4 mm. The results demonstrate an excellent potential of the eWLB package concept for mm-wave applications. The measured gain of the packaged mixer is in best case only 1 dB smaller than measured on-wafer. Further, we analyze the transition from the printed circuit board (PCB) to the chip in package. We compare the results of our analysis with the measured performance of the packaged mixers. We achieve a good agreement between simulations and measurements. Finally, we discuss the methods for improving the electrical performance of the packages assembled on the PCB.

Led driver with feedback calibration

Abstract: Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive a plurality of LED strings. An LED driver implements a feedback mechanism to monitor the tail voltages of the active LED strings to identify the minimum tail voltage and adjust the output voltage of the voltage source based on the lowest tail voltage. A loop calibration module of the LED driver calibrates the feedback mechanism of the LED driver based on a relationship between a digital code value used to generate a particular output voltage and another digital code value generated based on the minimum tail voltage resulting from the particular output voltage.

High bandwidth cache-to-processing unit communication in a multiple processor/cache system

Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

Multilayered through via

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

Abstract: We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

Uplink control channel allocation

Abstract: Various methods of allocating uplink control channels in a communication system (100) are implemented at a resource scheduler (107) or a user equipment (UE) (103, 105). In one method the scheduler (107) reserves resources for a downlink data channel (305) and signals a corresponding downlink data channel grant (311) and also reserves resources for a persistent uplink control channel (307) for a longer duration than the data channel grant. Signaling overhead associated with a grant for this persistent uplink control channel is reduced over a full dynamic grant. A predetermined rule (407) can be used at the scheduler and at the UE to avoid overhead signaling associated with a grant for this persistent control channel. Predetermined rules at the UE and scheduler can also be used to reserve appropriate resources (409) and select appropriate MCS levels for control information and the control information and uplink data can be transported over a common uplink channel when a time overlap occurs between an uplink data channel and the persistent control channel.

Reducing power consumption in a portable electronic device with a luminescent element

Abstract: A portable device including at least one luminescent element, a camera including an image sensor for activation to produce an electrical image signal representative of an image sensed by the image sensor, and a camera signal processor including a camera memory for storing the image signal for subsequent reproduction of the image, the device also including a luminescence controller for controlling a brightness of the luminescent element, the camera signal processor is also arranged to activate the image sensor intermittently to produce sample signals representative of ambient light during periods in which the image signal is not being stored in the camera memory, the luminescence controller being responsive to the sample signals to modulate progressively the brightness of the luminescent element as a function of a brightness of ambient light. In a portable device including at least one luminescent element, a plurality of human-interface actuators, at least one sensor responsive to an ambient variable relating to usage of the device, a timer and an activation controller for controlling activation and deactivation of the luminescent element, the activation controller is responsive to different conjunctions of signals from the actuators, the sensor and the timer to activate selectively and to extinguish the luminescent element, whereby to economise power consumption of the luminescent element when the conjunction of signals is indicative of user inactivity of the device.

Thermal modeling and design of 3D integrated circuits

Abstract: 3D interconnect technology has attracted significant interest in the recent past as a means for enabling faster and more efficient integrated circuits (ICs). 3D integration relies on through-silicon vias (TSVs) and bonding of multiple active layers. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in 3D electronic circuits are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the 3D technology, including thermal resistance of bonding layers and TSVs. As a result, an improved bonding layer or TSV thermal resistance does not offer much thermal benefit. An increase in thermal resistance of a 3D IC is predicted as compared to an equivalent System-on-Chip (SoC). This increase is found to be mainly due to the reduced chip footprint. The amount of improvement required in package and heat sink thermal resistances for a logic-on-memory 3D implementation to be thermally feasible is quantified. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3D ICs.

Method for forming a through silicon via layout

Abstract: A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.

Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

Abstract: Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications which demand high-performance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

Abstract: A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

Packaging an integrated circuit die with backside metallization

Abstract: A method ( 32 ) of packaging integrated circuit (IC) dies ( 48 ) includes applying ( 36 ) a laminating material ( 44 ) to a wafer ( 40 ), and separating ( 46 ) the wafer ( 40 ) into multiple IC dies ( 48 ) such that the laminating material ( 44 ) is applied to back surfaces ( 52 ) of the IC dies ( 48 ). Each of the IC dies ( 48 ) is positioned ( 62 ) with an active surface ( 50 ) facing a support substrate ( 56 ). An encapsulant layer ( 72 ) is formed ( 64 ) overlying the laminating material ( 44 ) and the back surfaces ( 52 ) of the IC dies ( 48 ) from a molding compound ( 66 ). The molding compound ( 66 ) and the laminating material ( 44 ) are removed from the back surfaces ( 52 ) of the IC dies ( 48 ) to form ( 76 ) openings ( 78 ) exposing the back surfaces ( 52 ). Conductive material ( 84, 88 ) is placed in the openings ( 78 ) and functions as a heat sink and/or a ground for the IC dies ( 48 ).