Journal ArticleDOI
BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs
Avirup Dasgupta,Shivendra Singh Parihar,Pragya Kushwaha,Harshit Agarwal,Ming-Yen Kao,Sayeef Salahuddin,Yogesh Singh Chauhan,Chenming Hu +7 more
TLDR
In this paper, the authors proposed a compact model for nanosheet FETs that takes the effects of quantum confinement into account, and implemented it using Verilog-A in the BSIM-CMG framework for all simulations.Abstract:
We propose a compact model for nanosheet FETs that take the effects of quantum confinement into account. The model captures the nanosheet width and thickness dependence of the electrostatic dimension, density of states, effective mass, subband energies, and threshold voltages and includes them in the charge calculation, resulting in an accurate terminal charge and current characteristics. The model has been implemented using Verilog-A in the BSIM-CMG framework for all simulations. It has been validated with band-structure calculation-based TCAD simulations as well as measured data. We have also highlighted the significance of quantum mechanical effects on analog and RF performance of the device.read more
Citations
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Journal ArticleDOI
Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study
J. Ajayan,D. Nirmal,Shubham Tayal,Sandip Bhattacharya,L. Arivazhagan,A. S. Augustine Fletcher,P. Murugapandiyan,D. Ajitha +7 more
TL;DR: It can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore's Law alive.
Journal ArticleDOI
Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors
TL;DR: In this paper, the negative capacitance effect of gate-all-around (GAA) nanosheet (NS) field effect transistors (FETs) was explored in silicon NS transistors by using TCAD.
Journal ArticleDOI
A Comprehensive Investigation of Vertically Stacked Silicon Nanosheet Field Effect Transistors: an Analog/RF Perspective
Shubham Tayal,J. Ajayan,L. M. I. Leo Joseph,J. Tarunkumar,D. Nirmal,Biswajit Jena,Ashutosh Nandi +6 more
TL;DR: In this paper, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) is investigated using 3-dimensional TCAD simulations.
Journal ArticleDOI
Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width.
Yuye Kang,Shengqiang Xu,Kaizhen Han,Eugene Y.-J. Kong,Zhigang Song,Sheng Luo,Annie Kumar,Chengkuan Wang,Weijun Fan,Gengchiau Liang,Xiao Gong +10 more
TL;DR: In this article, the authors demonstrate Ge0.95Sn0.05 gate-all-around field effect transistors (p-GAAFETs) with sub-3 nm nanowire width (WNW) on a GeSn-on-insulator (GeSnOI) substrate using a top-down fabrication process.
References
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Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Proceedings ArticleDOI
Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires
Kyoung Hwan Yeo,Sung Dae Suk,Ming Li,Yun-Young Yeoh,Keun Hwi Cho,Ki-Ha Hong,Seong-Kyu Yun,Mong Sup Lee,Nammyun Cho,Kwan-Heum Lee,Duhyun Hwang,Bokkyoung Park,Dong-Won Kim,Donggun Park,Byung-Il Ryu +14 more
TL;DR: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity in this article, which shows high driving current of 1.94 mA/?m.
Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Proceedings ArticleDOI
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
Hans Mertens,Romain Ritzenthaler,Adrian Chasin,Tom Schram,Eddy Kunnen,Andriy Hikavyy,Lars-Ake Ragnarsson,Harold Dekkers,T. Hopf,Kurt Wostyn,Katia Devriendt,S. A. Chew,Min-Soo Kim,Y. Kikuchi,Erik Rosseel,G. Mannaert,Stefan Kubicek,Steven Demuynck,A. Dangol,N. Bosman,J. Geypen,Patrick Carolan,Hugo Bender,Kathy Barla,Naoto Horiguchi,Dan Mocuta +25 more
TL;DR: In this paper, the authors report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V t, sat ∼ 0.35 V) for N- and P-type devices.
Journal ArticleDOI
Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode
TL;DR: In this paper, the authors derived an analytical model for the electrostatics and the drive current in a silicon nanowire operating in JFET mode, and showed that there exists a range of nanowires radii and doping densities for which the nan-wire JFet satisfies reasonable device characteristics.
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