Journal ArticleDOI
Silicon integrated circuit technology from past to future
Hiroshi Iwai,Shu N.ichiro Ohmi +1 more
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TLDR
Progress of silicon IC technologies for the past 30 years is described at first, the difficulties of the further downsizing for future are explained in detail, and the efforts to solve difficulties and the possible solutions are described.About:
This article is published in Microelectronics Reliability.The article was published on 2002-04-01. It has received 96 citations till now. The article focuses on the topics: Integrated circuit.read more
Citations
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Journal ArticleDOI
On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors
Hei Wong,Hei Wong,Hiroshi Iwai +2 more
TL;DR: In this article, the authors reviewed several critical issues of MOS gate dielectrics in the nanometer range and suggested that the conventional oxide can be scaled down, in principle, to two atomic layers of about 7 A, but this is not practically feasible because of the non-scalabilities of interface, trap capture cross-section, leakage current, and the statistical parameters of fabrication processes.
Journal ArticleDOI
Navigation aids in the search for future high-k dielectrics: Physical and electrical trends
Olof Engström,Bahman Raeissi,Steve Hall,Octavian Buiu,Max C. Lemme,Heiner Gottlob,Paul K. Hurley,Karim Cherkaoui +7 more
TL;DR: In this article, empirical relations for k-values and energy band offset values for gate dielectric materials are presented, which can be used in the search for gate-dielectric material fulfilling the needs of future CMOS generations.
Journal ArticleDOI
‘Old Chemistries’ for new applications: Perspectives for development of precursors for MOCVD and ALD applications
TL;DR: In this paper, the concept of utilizing "old chemistries" for new CVD and ALD applications was highlighted focussing on some representative functional materials namely group IV and rare earth oxides.
Navigation aids in the search for future high-k dielectrics: physical and electrical trends
Olof Engström,Bahman Raeissi,Steve Hall,Octavian Buiu,Max C. Lemme,Heiner Gottlob,Paul K. Hurley,Karim Cherkaoui +7 more
TL;DR: In this article, empirical relations for k-values and energy band offset values for gate dielectric materials are presented, which can be used in the search for gate-dielectric material fulfilling the needs of future CMOS generations.
Journal ArticleDOI
Atomic-layer deposition of Lu2O3
Giovanna Scarel,Emiliano Bonera,Claudia Wiemer,G. Tallarida,Sabina Spiga,Marco Fanciulli,Igor L. Fedushkin,H. Schumann,Yu. Yu. Lebedinskii,Andrei Zenkevich +9 more
TL;DR: In this article, the growth by atomic-layer deposition of lutetium oxide films using the dimeric {[C5H4(SiMe3)]2LuCl}2 complex, which has been synthesized for this purpose, and H2O was reported.
References
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Journal ArticleDOI
Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Proceedings ArticleDOI
Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology
Daniel C. Edelstein,John E. Heidenreich,Ronald D. Goldblatt,William J. Cote,Cyprian E. Uzoh,Naftali E. Lustig,Peter Roper,Thomas L. McDevitt,W. Motsiff,A. Simon,J. Dukovic,Richard A. Wachnik,H. Rathore,R. Schulz,L. Su,Stephen E. Luce,J. Slattery +16 more
TL;DR: In this paper, the first fully integrated ULSI CMOS/copper interconnect technology is presented, where up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a poly-contacting pitch of 1.81 /spl µ/m.
Proceedings ArticleDOI
Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application
TL;DR: Physical, electrical and reliability characteristics of ultra thin HfO/sub 2/ as an alternative gate dielectric were studied for the first time in this article, where the process parameters of oxygen modulated dc magnetron sputtering were optimized to achieve an equivalent oxide thickness (EOT) of 11.5 /spl Aring/ without deducting the quantum mechanical effect.
Proceedings ArticleDOI
A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization
Suresh Venkatesan,A.V. Gelatos,B. Smith,R. Islam,J. Cope,B. Wilson,D. Tuttle,R. Cardwell,S. Anderson,M. Angyal,R. Bajaj,C. Capasso,P. Crabtree,Saroj Das,J. Farkas,Stanley M. Filipiak,B. Fiordalice,Melissa Freeman,Percy V. Gilbert,M. Herrick,Ajay Jain,H. Kawasaki,Charles Fredrick King,Jeffrey L. Klein,T. Lii,Kimberly G. Reid,T. Saaranen,Cindy Reidsema Simpson,T. Sparks,Paul G. Y. Tsui,R. Venkatraman,David K. Watts,E.J. Weitzman,R. Woodruff,I. Yang,Navakanta Bhat,Gregory Norman Hamilton,Y. Yu +37 more
TL;DR: In this paper, a high performance 020 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects, optimized for 18 V operation to provide high performance with low power-delay products and excellent reliability.
Proceedings ArticleDOI
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
TL;DR: In this article, the authors investigate scaling challenges and outline device design requirements needed to support high performance low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm.