Showing papers on "Leakage (electronics) published in 2010"

A review of methods for leakage management in pipe networks

Abstract: Leakage in water distribution systems is an important issue which is affecting water companies and their customers worldwide. It is therefore no surprise that it has attracted a lot of attention by both practitioners and researchers over the past years. Most of the leakage management related methods developed so far can be broadly classified as follows: (1) leakage assessment methods which are focusing on quantifying the amount of water lost; (2) leakage detection methods which are primarily concerned with the detection of leakage hotspots and (3) leakage control models which are focused on the effective control of current and future leakage levels. This paper provides a comprehensive review of the above methods with the objective to identify the current state-of-the-art in the field and to then make recommendations for future work. The review ends with the main conclusion that despite all the advancements made in the past, there is still a lot of scope and need for further work, especially in area of rea...

Ultralow-Power Design in Near-Threshold Region

Abstract: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

Modulation Techniques to Eliminate Leakage Currents in Transformerless Three-Phase Photovoltaic Systems

Abstract: In some photovoltaic (PV) applications, it is possible to remove the transformer of a system in order to reduce losses, cost, and size. In transformerless systems, the PV module parasitic capacitance can introduce leakage currents in which the amplitude depends on the converter topology, on the pulsewidth modulation, and on the resonant circuit comprised by the system components. Based on the common-mode voltage model, modulation techniques are proposed to eliminate the leakage current in transformerless PV systems without requiring any modification on the converter and any additional hardware. The main drawback is that the proposed modulation technique for two-level inverters can only be used with 650-V dc link in the case of a 110-V (rms) grid phase voltage. Comparisons among the modulation techniques are discussed, and it is proven that the proposed modulation for two- and three-level inverters presents the best results. To validate the models used in the simulations, an experimental three-phase inverter is used.

Leakage in Nanometer CMOS Technologies

Abstract: Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles. Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions. Case studies supply real-world examples that reap the benefits of leakage power reduction solutions as the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

Abstract: As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

Temperature-Dependent $I$ – $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Tunnel FET

Abstract: We report on the experimental temperature-dependent characteristics of vertical In0.53Ga0.47As tunnel field-effect transistors (TFETs) at low drain bias to provide key insight into its device operation and design. Leakage floor (IOFF) is determined by the ungated p+-i-n+ reverse bias leakage and is dominated by Shockley-Read-Hall generation-recombination current. The temperature dependence of subthreshold slope arises from tunneling into mid-gap states at the oxide-semiconductor interface, followed by thermal emission into the conduction band. At intermediate gate voltages, pure band-to-band tunneling dominates, while at higher gate voltages, current transport is diffusion limited. The temperature-dependent study of In0.53Ga0.47As TFET highlights the importance of passivating the III-V and dielectric interface.

Universality of non-ohmic shunt leakage in thin-film solar cells

Abstract: We compare the dark current-voltage (IV) characteristics of three different thin-film solar cell types: hydrogenated amorphous silicon (a-Si:H) p-i-n cells, organic bulk heterojunction (BHJ) cells, and Cu(In,Ga)Se2 (CIGS) cells. All three device types exhibit a significant shunt leakage current at low forward bias (V<∼0.4) and reverse bias, which cannot be explained by the classical solar cell diode model. This parasitic shunt current exhibits non-Ohmic behavior, as opposed to the traditional constant shunt resistance model for photovoltaics. We show here that this shunt leakage (Ish), across all three solar cell types considered, is characterized by the following common phenomenological features: (a) voltage symmetry about V=0, (b) nonlinear (power law) voltage dependence, and (c) extremely weak temperature dependence. Based on this analysis, we provide a simple method of subtracting this shunt current component from the measured data and discuss its implications on dark IV parameter extraction. We propo...

On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors

Abstract: Tunneling field-effect transistors (TFETs) have gained a great deal of interest recently due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been to achieve high drive currents, which is a prerequisite for high-performance operation. In this paper, we explore the performance potential of a 1-D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, as well as the carbon nanotube band structure as the model 1-D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation and show that it can, indeed, produce less than 60 mV/dec subthreshold swing at room temperature, even in the presence of electron-phonon scattering. The 1-D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.

Three-terminal field effect devices utilizing thin film vanadium oxide as the channel layer

Abstract: Electrostatic control of the metal-insulator transition (MIT) in an oxide semiconductor could potentially impact the emerging field of oxide electronics. Vanadium dioxide (VO2) is of particular interest due to the fact that the MIT happens in the vicinity of room temperature and it is considered to exhibit the Mott transition. We present a detailed account of our experimental investigation into three-terminal field effect transistor-like devices using thin film VO2 as the channel layer. The gate is separated from the channel through an insulating gate oxide layer, enabling true probing of the field effect with minimal or no interference from large leakage currents flowing directly from the electrode. The influence of the fabrication of multiple components of the device, including the gate oxide deposition, on the VO2 film characteristics is discussed. Further, we discuss the effect of the gate voltage on the device response, point out some of the unusual characteristics including temporal dependence. A re...

Compact broadband polarizer based on shallowly-etched silicon-on-insulator ridge optical waveguides

Abstract: A new way to make broadband polarizers on silicon-on-insulator (SOI) waveguides is proposed, analyzed and characterized. The characteristics of the eigenmodes in a shallowly-etched SOI ridge optical waveguide are analyzed by using a full-vectorial finite-different method (FV-FDM) mode solver. The theoretical calculation shows that the loss of TE fundamental mode could be made very low while at the same time the TM fundamental mode has very large leakage loss, which is strongly dependent on the trench width. The leakage loss of the TM fundamental mode changes quasi-periodically as the trench width w(tr) varies. The formula of the period ∆w(tr) is given. By utilizing the huge polarization dependent loss of this kind of waveguide, a compact and simple optical polarizer based on a straight waveguide was demonstrated. The polarizer is fabricated on a 700 nm-thick SOI wafer and then characterized by using a free-space optical system. The measured extinction ratio is as high as 25 dB over a 100 nm wavelength range for a 1 mm-long polarizer.

Oxygen concentration and its effect on the leakage current in BiFeO3 thin films

Abstract: Epitaxial c-axis oriented BiFeO3 (BFO) films were fabricated on (001) oriented SrTiO3 substrates by pulsed laser deposition. Nuclear resonance backscattering spectrometry was used to directly measure the oxygen concentration of as-deposited and annealed BFO films. Compared to the ideal stoichiometry of BFO, the as-deposited BFO film shows more than 10% oxygen deficiency. However, postannealing the as-deposited BFO films reduces the oxygen deficiency almost half. The reduced oxygen vacancies in annealed BFO films are believed to be responsible for the different leakage mechanisms and the two orders of magnitude drop in leakage current density.

Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications

Abstract: This letter presents the design of a tunneling FET with III-V-based tunnel heterojunctions for operation in digital circuits with supply voltages as low as 0.3 V. A representative implementation is predicted to achieve an on-state current drive of 0.4 mA/?m with an off-state current of 50 nA/?m. Comparison with homojunction counterparts reveals that the hetero-tunnel-junction implementations may address better the design tradeoff between on-state drive and off-state leakage.

AlGaN/GaN/AlGaN DH-HEMTs Breakdown Voltage Enhancement Using Multiple Grating Field Plates (MGFPs)

Abstract: GaN-based high-electron mobility transistors with planar multiple grating field plates (MGFPs) for high-voltage operation are described. A synergy effect with additional electron channel confinement by using a heterojunction AlGaN back barrier (BB) is demonstrated. Suppression of the OFF-state subthreshold gate and drain leakage currents enables breakdown voltage enhancement over 700 V and a low ON-state resistance of 0.68 mΩ × cm2. Such devices have a minor tradeoff in ON-state resistance, lag factor, maximum oscillation frequency, and cutoff frequency. A systematic study of the MGFP design and the effect of Al composition in the BB is described. Physics-based device simulation results give insight into electric field distribution and charge carrier concentration, depending on the field plate design.

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Abstract: We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

On the possibility of obtaining MOSFET-like performance and sub-60 mV/decade swing in 1D broken-gap tunnel transistors

Abstract: Tunneling field-effect transistors (TFETs) have gained a great deal of recent interest due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been achieving high drive currents, which is a prerequisite for high-performance operation. In this paper we explore the performance potential of a 1D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, and the carbon nanotube bandstructure as the model 1D material system. We provide detailed insights into broken-gap TFET (BG-TFET) operation, and show that it can indeed produce less than 60mV/decade subthreshold swing at room temperature even in the presence of electron-phonon scattering. The 1D geometry is recognized to be uniquely favorable due to its superior electrostatic control, reduced carrier thermalization rate, and beneficial quantum confinement effects that reduce the off-state leakage below the thermionic limit. Because of higher source injection compared to staggered-gap and homojunction geometries, BG-TFET delivers superior performance that is comparable to MOSFET's. BG-TFET even exceeds the MOSFET performance at lower supply voltages (VDD), showing promise for low-power/high-performance applications.

Process Conditions for Improvement of Electrical Properties of Al2O3/n-GaN Structures Prepared by Atomic Layer Deposition

Abstract: The effects of fabrication processes on the electrical properties of Al2O3/GaN structures prepared by atomic layer deposition were investigated. The annealing process at 800 °C for the formation of ohmic electrodes brought a large number of microcrystallization regions into the Al2O3 layer, causing a marked leakage in the current–voltage characteristics of the Al2O3/GaN structure. The "ohmic-first" process with a SiN protection layer was thus applied to the GaN surface. In this process, the amorphous phase in the atomic configuration of Al2O3 was maintained, leading to the sufficient suppression of leakage current at the Al2O3/GaN interface. In addition, the Al2O3/GaN structures showed good capacitance–voltage characteristics, resulting in low interface state densities of less than 1×1012 cm-2 eV-1.

“Charge Leakage” at LaMnO3/SrTiO3 Interfaces

Abstract: We report on the charge transfer at the interface between a band (SrTiO3) and a Mott insulator (LaMnO3) in epitaxial superlattices. We have used combined atomic resolution electron microscopy and spectroscopy, synchrotron X ray reciprocal space maps and magneto transport measurements, to characterize the interface properties. The LaMnO3 layers are always started and terminated in (LaO) planes, giving an overall electron doping to the system. However, the direction of charge leakage is determined by the manganite to titanate thickness ratio in a way controlled by the different epitaxial strain patterns. This result may provide a clue to optimize oxide devices such as magnetic tunnel junctions and field effect transistors whose operation is determined by the interface properties.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

Abstract: We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V T -variability performances are obtained (A VT =1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V DD =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ SNM DD =0.7V. We also demonstrate ultra-low leakage ( G = 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

Fully Transparent Non‐volatile Memory Thin‐Film Transistors Using an Organic Ferroelectric and Oxide Semiconductor Below 200 °C

Abstract: A fully transparent non-volatile memory thin-film transistor (T-MTFT) is demonstrated. The gate stack is composed of organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and oxide semiconducting Al-Zn-Sn-O (AZTO) layers, in which thin Al 2 O 3 is introduced between two layers. All the fabrication processes are performed below 200 °C on the glass substrate. The transmittance of the fabricated device was more than 90% at the wavelength of 550 nm. The memory window obtained in the T-MTFT was 7.5 V with a gate voltage sweep of —10 to 10 V, and it was still 1.8 V even with a lower voltage sweep of —6 to 6 V. The field-effect mobility, subthreshold swing, on/off ratio, and gate leakage currents were obtained to be 32.2 cm 2 V ―1 s ―1 , 0.45 V decade ―1 , 10 8 , and 10 ―13 A, respectively. All these characteristics correspond to the best performances among all types of non-volatile memory transistors reported so far, although the programming speed and retention time should be more improved.

Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment

Abstract: With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fails to accurately address the impact of scaling on system power consumption as the leakage power increases exponentially. The combination of DVS and adaptive body biasing (ABB) is an effective technique to jointly optimize dynamic and leakage energy dissipation. In this paper, we propose an optimal soft real-time loop scheduling and voltage assignment algorithm, loop scheduling and voltage assignment to minimize energy, to minimize both dynamic and leakage energy via DVS and ABB. Voltage transition overhead has been considered in our approach. We conduct simulations on a set of digital signal processor benchmarks based on the power model of 70 nm technology. The simulation results show that our approach achieves significant energy saving compared to that of the integer linear programming approach.

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Abstract: Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this limitation, 7T SRAM designs were proposed earlier at the cost of extra silicon area. In this paper, we propose a novel 6T SRAM design using Si-TFETs for reliable operation with low leakage at ultra low voltages. We also demonstrate that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using proposed design when compared with the 7T TFET SRAM cell. We achieve a leakage reduction improvement of 700X and 1600X over traditional CMOS SRAM designs at V DD of 0.3V and 0.5V respectively which makes it suitable for use at ultra-low power applications.

A Wavelet-Based Approach to Internal Seal Damage Diagnosis in Hydraulic Actuators

Abstract: This paper describes the application of wavelet transform (WT) to detect internal leakage in hydraulic actuators, caused by seal damage. The method analyzes the pressure signal at one side of the actuator in response to periodic step inputs to the control valve. It is shown that the detailed version of decomposed pressure signal, using discrete WT, establishes feature patterns that can effectively detect internal leakage and its severity. The proposed scheme requires a baseline (threshold) value, predetermined first by analyzing the pressure signal of a healthy actuator. Once the root mean square (rms) of the level-two detail coefficient values, obtained from the measured pressure signals in subsequent offline tests, fall below this baseline, a fault alarm is triggered. Furthermore, the degree of changes of the rms value from the one obtained under normal operating condition indicates the severity of fault. Experimental tests show promising results for detecting internal leakages as low as 0.124 L/min, representing approximately 2.6% reduction of flow rate available to move the actuator. This is done without a need to model the actuator or leakage. Other methods of leakage fault diagnosis require the model of the actuator or leakage fault. Furthermore, no other method reported the internal leakage detection of magnitude as low as the one reported in this paper.

Current deep level transient spectroscopy analysis of AlInN/GaN high electron mobility transistors: Mechanism of gate leakage

Abstract: In order to assess possible mechanisms of gate reverse-bias leakage current in AlInN/GaN high electron mobility transistors (HEMTs) grown by metalorganic chemical-vapor deposition on SiC substrates, temperature-dependent current-voltage measurements combined with Fourier transform current deep level transient spectroscopy (FT-CDLTS) are performed in the temperature range of 200–400 K. In this range of temperature reverse-bias leakage current flow is found to be dominated by Poole–Frenkel emission. Based on CDLTS measurements, a model of leakage current transport via a trap state located at the AlInN/metal interface with an activation energy of 0.37 eV is suggested. The trap nature is shown to be an extended trap, most probably associated with dislocations in the AlInN barrier layer.

Graphene for CMOS and Beyond CMOS Applications

Abstract: Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapor deposition, and field-effect devices have been demonstrated with room temperature field-effect mobilities close to 10 000 cm2/Vs. But since graphene is a gapless semiconductor, these transistors have high off-state leakage and nonsaturating drive currents. This is problematic for digital logic, but is acceptable for analog device applications such as low-noise amplifiers and radio-frequency (RF)/millimeter-wave field-effect transistors (FETs). The remarkable transport physics of graphene due to its linear bandstructure have led to novel beyond CMOS logic devices as well, such as “pseudospin” devices.

Improving optical confinement in nanostructures via external mode coupling.

Abstract: We demonstrate the formation of long-lived resonances via external coupling in open nanostructures. In the examples of three dielectric nanorods or strips, external coupling of modes is induced by tuning of the rod spacing and increases the lifetime over an order of magnitude. Such an enhancement results from the destructive interference of fields that minimizes light leakage. Our results illustrate an effective way of storing light in nanostructures, and have potential applications to nanoscale photonic devices.

Defect-related tunneling mechanism of efficiency droop in III-nitride light-emitting diodes

Abstract: The quantum efficiency of GaN-based light-emitting diodes (LEDs) is investigated at temperatures 77–300 K. It is found that the efficiency droop is due to a decrease in the internal quantum efficiency (IQE) in the low-energy part of the emission spectrum. The efficiency starts to decrease at a temperature independent forward voltage of Umax≈2.9 V. At this voltage tunneling current through the LED-structure begins to dominate. It is suggested that the external quantum efficiency droop is related to reduction of the IQE due to tunneling leakage of carriers from the quantum well (QW) to defect states in barriers, and to reduction of the injection efficiency by excess tunneling current under QW through deep defect states in barriers.

Coaxial through-silicon via

Abstract: A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.

Dynamics of CO2 fluxes and concentrations during a shallow subsurface CO2 release.

Abstract: A field facility located in Bozeman, Montana provides the opportunity to test methods to detect, locate, and quantify potential CO2 leakage from geologic storage sites. From 9 July to 7 August 2008, 0.3 t CO2 day−1 were injected from a 100-m long, ~2.5-m deep horizontal well. Repeated measurements of soil CO2 fluxes on a grid characterized the spatio-temporal evolution of the surface leakage signal and quantified the surface leakage rate. Infrared CO2 concentration sensors installed in the soil at 30 cm depth at 0–10 m from the well and at 4 cm above the ground at 0 and 5 m from the well recorded surface breakthrough of CO2 leakage and migration of CO2 leakage through the soil. Temporal variations in CO2 concentrations were correlated with atmospheric and soil temperature, wind speed, atmospheric pressure, rainfall, and CO2 injection rate.

Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistors

Abstract: Using an atomistic full-band quantum transport solver, we investigate the performances of vertical band-to-band tunneling FETs (TFETs) whose operation is based on the enhancement of the gate-induced drain leakage mechanism of MOSFETs, and we compare them to lateral p-i-n devices. Although the vertical TFETs offer larger tunneling areas and therefore larger on currents than their lateral counterparts, they suffer from lateral source-to-drain tunneling leakage away from the gate contact. We propose a design improvement to reduce the off current of the vertical TFETs, maintain large on currents, and provide steep subthreshold slopes.

Use of leakage currents of insulators to determine the stage characteristics of the flashover process and contamination level prediction

Abstract: In order to improve the reliability of power transmission lines, one of the key issues is to reduce the hazard of contamination flashovers. Presently, the most efficient way is to clean (or replace) the heavily polluted insulators. The leakage current is the critical online quantity that can be detected. A number of laboratory experiments on 35 kV voltage class ceramic and glass insulators show that the leakage current fully reflects the entire process of contamination flashover development. The test results reveal that the process can be classified into three stages, i.e., security stage, forecast stage and danger stage. The results, that were duplicated several times, are based on three characteristics of the leakage current, i.e., the root-mean-square value, waveforms, and power spectrum estimation. In addition, the boundaries of the three stages in both time domain and power spectrum domain are also determined. All these can be used for the stage pre-warning of contamination flashovers. The security stage is most important since it precedes the contamination flashover sufficiently. The three characteristics of the leakage current in the security stage are proposed as the inputs of a neural network model together with the operating voltage, and the relative humidity in order to determine the equivalent salt deposit density (ESDD) of the insulators. The comparison of the simulated and actual (measured) results demonstrates that the ESDD prediction model has a very low relative error if the training data and the testing data both come from the security stage. The application of this research results in (1) optimal ESDD prediction inputs and (2) sufficient pre-warning time before the ultimate contamination flashover.