Showing papers on "Leakage (electronics) published in 2011"

An Efficient High-Step-Up Interleaved DC–DC Converter With a Common Active Clamp

Abstract: This paper presents a high-efficiency and high-step-up nonisolated interleaved dc-dc converter with a common active-clamp circuit. In the presented converter, the coupled-inductor boost converters are interleaved. A boost converter is used to clamp the voltage stresses of all the switches in the interleaved converters, caused by the leakage inductances present in the practical coupled inductors, to a low voltage level. The leakage energies of the interleaved converters are collected in a clamp capacitor and recycled to the output by the clamp boost converter. The proposed converter achieves high efficiency because of the recycling of the leakage energies, reduction of the switch voltage stress, mitigation of the output diode's reverse recovery problem, and interleaving of the converters. Detailed analysis and design of the proposed converter are carried out. A prototype of the proposed converter is developed, and its experimental results are presented for validation.

CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

Abstract: This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.

An electronic vaporisation cigarette

Abstract: The present invention relates to an electronic vaporisation cigarette, comprising: a shell (100); a mouthpiece including a cap (201) and a ring (203), detachably attached at an anterior end (101) of the shell (100); an absorbent means (300) having liquid absorbed therein; a vaporiser including a heating element (401) and an insulator for vaporising the liquid when said vaporiser is electrically heated, wherein the vaporiser is in proximity with the absorbent means (300); a battery (700) to supply electrical energy for heating the heating element (401); a switch base (800) connected to the battery (700) to switch on the battery (700); and a cover (900) detachably attached at a posterior end (102) of the shell (100); characterised in that: a liquid segregate base (500) and a plate (600) are in proximity with the vaporiser for preventing leakage of the liquid; the cover (900) has a plurality of air inlets (901); and the switch base (800) is in proximity with the cover (900) and has a plurality of holes (801) to receive wires (11) and allow from the plurality of air inlets (901) to the vaporiser.

Low/high frequency shared leakage antenna, base station apparatus and close-range detection system using the antenna

Abstract: The present invention provides a high/low frequency dual wireless location detection and information transmission system which is high in reliability and maintainability, and can be easily installed. A leakage coaxial inner conductor and a conductor line provided in parallel are short-circuited at an end, a single leakage coaxial operation and a loop operation of the inner conductor and the conductor line are performed at the same time, the ID of a tag is communicated using magnetic fields which locally exist near the conductor line by the loop, and wireless position detection and information communications which are less affected by the influence of ambient environments due to electromagnetic waves in a closed area are realized by open-type lines.

Native defects in Al2O3 and their impact on III-V/Al2O3 metal-oxide-semiconductor-based devices

Abstract: Al2O3 is a promising material for use as a dielectric in metal-oxide-semiconductor devices based on III-V compound semiconductors. However, the presence of deep levels and fixed charge in the Al2O3 layer is still a concern, with native defects being a possible cause of traps, leakage, and fixed charge. We report hybrid density functional calculations for vacancies, self-interstitials, and antisites in Al2O3. The energetic positions of defect levels are discussed in terms of the calculated band alignment at the interface between the oxide and relevant III-V materials. We find that oxygen vacancies are the defects most likely to introduce gap levels that may induce border traps or leakage current in a gate stack. In addition, both self-interstitials and aluminum vacancies introduce fixed charge that leads to increased carrier scattering in the channel and shifts the threshold voltage of the device.

Modulation for Three-Phase Transformerless Z-Source Inverter to Reduce Leakage Currents in Photovoltaic Systems

Abstract: In this paper, a modified Z-source inverter (ZSI) with specific modulation techniques is proposed to reduce leakage currents in three-phase transformerless photovoltaic (PV) systems. The new topology only requires an additional fast-recovery diode when compared with the original structure. On the other hand, the pulsewidth modulation technique is entirely modified in order to reduce the leakage currents through the conduction path. Simulation results for the three-phase transformerless PV system operating in two cases, i.e., connected to a grid and connected to a grounded RL load, are presented. Experimental results of leakage currents in three-phase ZSIs connected to a RL load are obtained to validate the theoretical and simulation models.

Graphene field-effect transistors

Abstract: Owing in part to scaling challenges for metal oxide semiconductor field-effect transistors (MOSFETs) and complementary metal oxide semiconductor (CMOS) logic, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide improved MOSFET performance beyond the 22 nm node, or provide novel functionality for, e.g. 'beyond CMOS' devices. Graphene, with its novel and electron–hole symmetric band structure and its high carrier mobilities and thermal velocities, is one such material that has garnered a great deal of interest for both purposes. Single and few layer carbon sheets have been fabricated by a variety of techniques including mechanical exfoliation and chemical vapour deposition, and field-effect transistors have been demonstrated with room-temperature mobilities as high as 10 000 cm2 V−1 s−1. But graphene is a gapless semiconductor and gate control of current is challenging, off-state leakage currents are high, and current does not readily saturate with drain voltage. However, various ways to overcome, adapt to, or even embrace this property are now being considered for device applications. In this work we explore through illustrative examples the potential of and challenges to graphene use for conventional and novel device applications.

Patterned radial GaAs nanopillar solar cells.

Abstract: Photovoltaic devices using GaAs nanopillar radial p–n junctions are demonstrated by means of catalyst-free selective-area metal–organic chemical vapor deposition. Dense, large-area, lithographically defined vertical arrays of nanowires with uniform spacing and dimensions allow for power conversion efficiencies for this material system of 2.54% (AM 1.5 G) and high rectification ratio of 213 (at ±1 V). The absence of metal catalyst contamination results in leakage currents of ∼236 nA at −1 V. High-resolution scanning photocurrent microscopy measurements reveal the independent functioning of each nanowire in the array with an individual peak photocurrent of ∼1 nA at 544 nm. External quantum efficiency shows that the photocarrier extraction highly depends on the degenerately doped transparent contact oxide. Two different top electrode schemes are adopted and characterized in terms of Hall, sheet resistance, and optical transmittance measurements.

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

Abstract: SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

Grain boundary-driven leakage path formation in HfO2 dielectrics

Abstract: The evolution over time of the leakage current in HfO 2 -based MIM capacitors under continuous or periodic constant voltage stress (CVS) was studied for a range of stress voltages and temperatures. The data were analyzed based on the results of conductive atomic force microscopy (AFM) measurements demonstrating preferential current flow along grain boundaries (GBs) in the HfO 2 dielectric and ab initio calculations, which show the formation of a conductive sub-band due to the precipitation of oxygen vacancies at the GBs. The simulations using the statistical multi-phonon trap-assisted tunneling (TAT) current description successfully reproduced the experimental leakage current stress time dependency by using the calculated energy characteristics of the O-vacancies. The proposed model suggests that the observed reversible increase in the stress current is caused by segregation of the oxygen vacancies at the GBs and their conversion to the TAT-active charge state caused by reversible electron trapping during CVS.

Buffer Thickness Contribution to Suppress Vertical Leakage Current With High Breakdown Field (2.3 MV/cm) for GaN on Si

Abstract: Vertical breakdown studies on AlGaN/GaN high-electron-mobility transistors (HEMTs) grown by metal-organic chemical vapor deposition (MOCVD) on a silicon substrate are studied to analyze the breakdown dependence with regard to i-GaN thickness (TGaN) and buffer thickness (TBuf). A high breakdown field (Ec) of 2.3 MV/cm was observed for MOCVD grown epilayers of total thickness of 5.5 μm on Si. Increasing TBuf is more significant than TGaN toward controlling the vertical leak age and demonstrates a high breakdown. For transistor operation at high voltages, GaN layers grown on thick buffers are highly resistive to the flow of leakage currents. A high figure of merit (BV2/Rd.ON) of 5.4 × 108 V2 · Ω-1· cm-2 was observed for an AlGaN/GaN HEMT grown on Si using a thick buffer.

FinFET Circuit Design

Abstract: Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate devices. The two gates of a FinFET can either be shorted for higher perfomance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space. This chapter provides an introduction to various interesting FinFET logic design styles, novel circuit designs, and layout considerations.

Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling

Abstract: We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current I D . We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured I D over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/ f 2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.

Reduced surface leakage current and trapping effects in AlGaN/GaN high electron mobility transistors on silicon with SiN/Al2O3 passivation

Abstract: The surface leakage currents and the surface trapping effects of the AlGaN/GaN high electron mobility transistors (HEMTs) on silicon with different passivation schemes, namely, a 120 nm plasma enhanced chemical vapor deposited SiN, a 10 nm atomic layer deposited (ALD) Al2O3 and a bilayer of SiN/Al2O3 (120/10 nm) have been investigated. After SiN passivation, the surface leakage current of the GaN HEMT was found to increase by about six orders; while it only increased by three orders after the insertion of Al2O3 between SiN and AlGaN/GaN. The surface conduction mechanism is believed to be the two-dimensional variable range hopping for all the samples. The leakage current in the etched GaN buffer layer with SiN/Al2O3 bilayer passivation was also much smaller than that with only SiN passivation. The pulse measurement shows that the bilayer of SiN/Al2O3 passivation scheme can effectively reduce the surface states and suppress the trapping effects.

Asymmetric Drain Spacer Extension (ADSE) FinFETs for Low-Power and Robust SRAMs

Abstract: In this paper, we analyze and optimize FinFETs with asymmetric drain spacer extension (ADSE) that introduces a gate underlap only on the drain side. We present a physics-based discussion of current-voltage relationships, short channel effects, and leakage and show the application of ADSE FinFETs in 6T static random access memory (SRAM) bit cell. By exploiting asymmetry in current, we show that it is possible to achieve improvement in both read and write stability for the 6T SRAM bit cell, along with reduction in cell leakage at the cost of negligible increase in access time and area. We also propose a general circuit-aware device optimization methodology for SRAM design. We use this methodology to optimize the underlap in ADSE FinFETs. Compared to conventional FinFETs, we achieve 57% reduction in leakage, 11% improvement in read static-noise margin, and 6% improvement in write margin, with 7% increase in access time and cell area.

Single-electron heat diode: Asymmetric heat transport between electronic reservoirs through Coulomb islands

Abstract: We introduce a functional nanoscale device, a single-electron heat diode, consisting of two quantum dots or metallic islands coupled to electronic reservoirs by tunnel contacts. Electron transport through the system is forbidden but the capacitive coupling between the two dots allows electronic fluctuations to transmit heat between the reservoirs. When the reservoir temperatures are biased in the forward direction, heat flow is enabled by a four-step sequential tunneling cycle, while in the reverse-biased configuration this process is suppressed due to Coulomb blockade effects. In an optimal setup the leakage heat current in the reverse direction is only a few percent of the forward current.

A 65 nm 0.165 fJ/Bit/Search 256 $\,\times\,$ 144 TCAM Macro Design for IPv6 Lookup Tables

Abstract: Ternary content addressable memory (TCAM) is extensively adopted in network systems. As routing tables become larger, energy consumption and leakage current become increasingly important issues in the design of TCAM in nano-scale technologies. This work presents a novel 65 nm energy-efficient TCAM macro design for IPv6 applications. The proposed TCAM employs the concept of architecture and circuit co-design. To achieve an energy-efficient TCAM architecture, a butterfly match-line scheme and a hierarchy search-line scheme are developed to reduce significantly both the search time and power consumption. The match-lines are also implemented using noise-tolerant XOR-based conditional keepers to reduce not only the search time but also the power consumption. To reduce the increasing leakage power in advanced technologies, the proposed TCAM design utilizes two power gating techniques, namely super cut-off power gating and multi-mode data-retention power gating. An energy-efficient 256 × 144 TCAM macro is implemented using UMC 65 nm CMOS technology, and the experimental results demonstrate a leakage power reduction of 19.3% and an energy metric of the TCAM macro of 0.165 fJ/bit/search.

Influence of threading dislocation density on early degradation in AlGaN/GaN high electron mobility transistors

Abstract: Early stage degradation of AlGaN/GaN high electron mobility transistors (HEMTs) with different threading dislocation densities (TDDs) submitted to off-state voltage bias stress was studied. It was found that, for the stress conditions used, HEMTs with TDD ∼1010 cm−2 show pronounced degradation in terms of maximum drain current, gate-lag, and trap generation measured by drain current trapping characteristics, a slight degradation in gate leakage was observed also for HEMTs with TDD of ∼108 cm−2, and no significant degradation for devices with TDD in the ∼107 cm−2 range. The results illustrate the importance of TDD for degradation and reliability of AlGaN/GaN HEMTs.

Ultimate device scaling: Intrinsic performance comparisons of carbon-based, InGaAs, and Si field-effect transistors for 5 nm gate length

Abstract: We use a single, multi-dimensional, and atomistic quantum transport simulator to investigate how far carbon nanotube, graphene nanoribbon, InGaAs, and Si ultra-thin body and nanowire n-type field-effect transistors can be scaled and to understand the mechanisms that limit their miniaturization. Despite multiple leakage paths, non-planar devices with a multi-gate architecture and an extremely narrow cross section can be expected to still work as good switches, even with a 5 nm gate length, provided that they exhibit a large enough band gap and transport effective mass and that their gate contact can modulate the electrostatic potential of the source and drain extensions to effectively increase the gate length.

High-k dielectric Al2O3 nanowire and nanoplate field effect sensors for improved pH sensing

Abstract: Over the last decade, field-effect transistors (FETs) with nanoscale dimensions have emerged as possible label-free biological and chemical sensors capable of highly sensitive detection of various entities and processes. While significant progress has been made towards improving their sensitivity, much is yet to be explored in the study of various critical parameters, such as the choice of a sensing dielectric, the choice of applied front and back gate biases, the design of the device dimensions, and many others. In this work, we present a process to fabricate nanowire and nanoplate FETs with Al2O3 gate dielectrics and we compare these devices with FETs with SiO2 gate dielectrics. The use of a high-k dielectric such as Al2O3 allows for the physical thickness of the gate dielectric to be thicker without losing sensitivity to charge, which then reduces leakage currents and results in devices that are highly robust in fluid. This optimized process results in devices stable for up to 8 h in fluidic environments. Using pH sensing as a benchmark, we show the importance of optimizing the device bias, particularly the back gate bias which modulates the effective channel thickness. We also demonstrate that devices with Al2O3 gate dielectrics exhibit superior sensitivity to pH when compared to devices with SiO2 gate dielectrics. Finally, we show that when the effective electrical silicon channel thickness is on the order of the Debye length, device response to pH is virtually independent of device width. These silicon FET sensors could become integral components of future silicon based Lab on Chip systems.

Dark current filtering in unipolar barrier infrared detectors

Abstract: Control of dark current mechanisms is essential to improving the performance of infrared photodetectors and many other electronic devices. Unipolar barriers can readily be applied to practically and efficiently filter out multiple dark current components exhibited by infrared photodetectors. Via careful placement of unipolar barriers in a standard photodetector architecture, effective suppression of dark currents due to surface leakage, direct band-to-band tunneling, trap-assisted tunneling, and Shockley-Read-Hall generation is demonstrated. We present unipolar barrier photodiodes exhibiting six orders of magnitude improvement in RoA and near Auger-limited device performance.

Detection of word-line leakage in memory arrays: current based approach

Abstract: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

Investigation on the parallel operation of discrete SiC BJTs and JFETs

Abstract: This paper presents an analysis of single discrete silicon carbide (SiC) JFET and BJT devices and their parallel operation. The static and dynamic characteristics of the devices were obtained over a wide range of temperature to study the scaling of device parameters. The static parameters like on-resistance, threshold voltage, current gains, transconductance, and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. A detailed analysis of the dynamic current sharing between the paralleled devices during the switching transients and energy losses at different voltages and currents is also presented. The effect of the gate driver on the device transient behavior of the paralleled devices was studied, and it was shown that faster switching speeds of the devices could cause mismatches in current shared during transients.

Semiconductor memory device and manufacturing method thereof

Abstract: A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.

Leakage mechanism of cation -modified BiFeO3 thin film

Abstract: To investigate the leakage mechanisms in cation -substituted BiFeO3 (BFO) thin films, in Bi site or Fe site or both sites, Bi0.92La0.08FeO3, BiFe0.95Mn0.05O3, and Bi0.92La0.08Fe0.95Mn0.05O3 thin films were grown in situ by radio frequency magnetic sputtering on SrRuO3/SrTiO3(111) substrates, where the (111) orientation is established in all thin films. The variation in cation substitution results in different leakage behavior of BFO thin films. Space charge limited conduction and a grain boundary limited behavior are responsible for the leakage behavior of Bi0.92La0.08FeO3 and BiFe0.95Mn0.05O3 thin films in a low electric field region, respectively, while an interface-limited Fowler-Nordheim tunneling is involved in their leakage behavior in a high electric field region. In contrast, the leakage of Bi0.92La0.08Fe0.95Mn0.05O3 endures a transition from an Ohmic conduction to space charge limited conduction with increasing electric fields. The three thin films however show little temperature dependence of th...

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Abstract: Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

Electrical reliability and leakage mechanisms in highly resistive multiferroic La0.1Bi0.9FeO3 ceramics

Abstract: Multiferroic La0.1Bi0.9FeO3 (LBFO) ceramics with high resistivity were synthesized by using a modified rapid thermal process. The LBFO ceramics show very low leakage and low dielectric loss. Well saturated ferroelectric hysteresis loops and polarization switching currents have been observed. For a maximum applied electric field of 145 kV/cm, the remanent polarization is 17.8 μC/cm2 and the coercive filed is 75 kV/cm. The dominant conduction mechanism in the LBFO ceramics has been found to be the space-charge-limited current mechanism rather than the thermal excitation mechanism. Electrical reliability related to the fatigue and polarization retention of the LBFO ceramics has also been discussed with the leakage mechanisms.