Showing papers on "Nanoelectronics published in 2005"
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.
Abstract: Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moore's Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.
630 citations
TL;DR: The mean-field treatment of electron-nuclear interaction results in many qualitative breakdowns in the time-dependent Kohn-Sham (TDKS) density functional theory, but this problem is resolved by the trajectory surface-hopping TDKS approach, illustrated by the photoinduced electron injection from a molecular chromophore into TiO2, and the excited-state relaxation of the green fluorescent protein chromophores.
Abstract: The mean-field treatment of electron-nuclear interaction results in many qualitative breakdowns in the time-dependent Kohn-Sham (TDKS) density functional theory. Examples include current-induced heating in nanoelectronics, charge dynamics in quantum dots and carbon nanotubes, and relaxation of biological chromophores. The problem is resolved by the trajectory surface-hopping TDKS approach, which is illustrated by the photoinduced electron injection from a molecular chromophore into ${\mathrm{TiO}}_{2}$, and the excited-state relaxation of the green fluorescent protein chromophore.
557 citations
TL;DR: An extensive review of the current state of the art in nitrogen doping of carbon nanotubes, including synthesis techniques, and comparison with nitrogen doped carbon thin films and azofullerenes is presented.
Abstract: Nitrogen doping of single and multi-walled carbon nanotubes is of great interest both fundamentally, to explore the effect of dopants on quasi-1D electrical conductors, and for applications such as field emission tips, lithium storage, composites and nanoelectronic devices. We present an extensive review of the current state of the art in nitrogen doping of carbon nanotubes, including synthesis techniques, and comparison with nitrogen doped carbon thin films and azofullerenes. Nitrogen doping significantly alters nanotube morphology, leading to compartmentalised 'bamboo' nanotube structures. We review spectroscopic studies of nitrogen dopants using techniques such as X-ray photoemission spectroscopy, electron energy loss spectroscopy and Raman studies, and associated theoretical models. We discuss the role of nanotube curvature and chirality (notably whether the nanotubes are metallic or semiconducting), and the effect of doping on nanotube surface chemistry. Finally we review the effect of nitrogen on the transport properties of carbon nanotubes, notably its ability to induce negative differential resistance in semiconducting tubes.
441 citations
IBM1
TL;DR: In this article, three different carbon nanotube (CN) field effect transistor (CNFET) designs are compared by simulation and experiment, and the authors explore the possibility of using CNs as gate-controlled tunneling devices.
Abstract: Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.
320 citations
TL;DR: The growth of ordered arrays of vertically aligned silicon nanowires by molecular beam epitaxy using prepatterned arrays of gold droplets on Si(111) substrates is shown.
Abstract: Because of their importance in fundamental research and possible applications in nanotechnology and nanoelectronics, semiconductor nanowires have attracted much interest. In addition to the growth itself, the control of the size and location is an essential problem. Here we show the growth of ordered arrays of vertically aligned silicon nanowires by molecular beam epitaxy using prepatterned arrays of gold droplets on Si(111) substrates. The ordered arrays of gold particles were produced by nanosphere lithography.
266 citations
TL;DR: The ability to detect and analyse point defects, especially at very low concentrations, indicates the promise of this technique for quantitative process analysis, especially in nanoelectronics development.
Abstract: The prevailing conception of carbon nanotubes and particularly single-walled carbon nanotubes (SWNTs) continues to be one of perfectly crystalline wires. Here, we demonstrate a selective electrochemical method that labels point defects and makes them easily visible for quantitative analysis. High-quality SWNTs are confirmed to contain one defect per 4 μm on average, with a distribution weighted towards areas of SWNT curvature. Although this defect density compares favourably to high-quality, silicon single-crystals, the presence of a single defect can have tremendous electronic effects in one-dimensional conductors such as SWNTs. We demonstrate a one-to-one correspondence between chemically active point defects and sites of local electronic sensitivity in SWNT circuits, confirming the expectation that individual defects may be critical to understanding and controlling variability, noise and chemical sensitivity in SWNT electronic devices. By varying the SWNT synthesis technique, we further show that the defect spacing can be varied over orders of magnitude. The ability to detect and analyse point defects, especially at very low concentrations, indicates the promise of this technique for quantitative process analysis, especially in nanoelectronics development. A
251 citations
TL;DR: In this paper, the authors present an overview of the issues related to the integration of carbon nanotubes into microelectronics systems and discuss the problems associated with the construction of nanotube-based devices.
Abstract: This paper presents an overview of the issues related to the integration of carbon nanotubes into microelectronics systems. Particular emphasis is placed on the use of carbon nanotubes as on-chip wiring (interconnects) and active devices (transistors), the two main building blocks of current semiconductor circuits. The properties of state-of-the art devices are compared in order to test the viability of replacing silicon-based components with carbon nanotubes. Further, the problems associated with the construction of nanotube-based devices are discussed.
211 citations
TL;DR: In this article, the authors explore the high-frequency performance potential of carbon nantube field effect transistors (CNTFETs) and show that using an array of parallel nanotubes as the transistor channel reduces parasitic capacitance per tube.
Abstract: Self-consistent quantum simulations are used to explore the high-frequency performance potential of carbon nantube field-effect transistors (CNTFETs). The cutoff frequency expected for a recently reported CNT Schottky-barrier FET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel reduces parasitic capacitance per tube. Increasing tube density gives a large improvement of high-frequency performance when tubes are widely spaced and parasitic capacitance dominates but only a small improvement when the tube spacing is small and intrinsic gate capacitance dominates. Alternatively, using quasi-one-dimensional nanowires as source and drain contacts should significantly reduce parasitic capacitance and improve high-frequency performance. Ballistic CNTFETs should outperform ballistic Si MOSFETs in terms of the high-frequency performance limit because of their larger band-structure-limited velocity.
191 citations
TL;DR: In this article, vertically grown multiwalled carbon nanotubes (MWCNTs) from the prepatterned catalyst dots on the patterned device electrodes have been used.
Abstract: Electromechanical switching devices have been fabricated successfully employing vertically grown multiwalled carbon nanotubes (MWCNTs) from the prepatterned catalyst dots on the patterned device electrodes. The devices show various interesting switching characteristics depending on the length and the number of MWCNTs used. The device design not only simplifies the fabrication process, but also improves the integration density greatly. The device has a great potential in realizing technically viable nanoelectromechanical systems, such as switch, memory, fingers, or grippers.
183 citations
05 Jul 2005
TL;DR: The generality of this bottom-up assembly approach suggests the integration of diverse nanoscale building blocks on a variety of substrates, potentially enabling far-reaching advances in lightweight display, mobile computing, and information storage applications.
Abstract: The introduction of an ambient-temperature route for integrating high-mobility semiconductors on flexible substrates could enable the development of novel electronic and photonic devices with the potential to impact a broad spectrum of applications. Here we review our recent studies demonstrating that high-quality single-crystal nanowires (NWs) can be assembled onto flexible plastic substrates under ambient conditions to create FETs and light-emitting diodes. We also show that polymer substrates can be patterned through the use of a room temperature nanoimprint lithography technique for the general fabrication of hundred-nanometer scale features, which can be hierarchically patterned to the millimeter scale and integrated with semiconductor NWs to make high-performance FETs. The key to our approach is the separation of the high-temperature synthesis of single-crystal NWs from room temperature solution-based assembly, thus enabling fabrication of single-crystal devices on virtually any substrate. Silicon NW FETs on plastic substrates display mobilities of 200 cm/sup 2/-V/sup -1/-s/sup -1/, rivaling those of single-crystal silicon and exceeding those of state-of-the-art amorphous silicon and organic transistors currently used for flexible electronics. Furthermore, the generality of this bottom-up assembly approach suggests the integration of diverse nanoscale building blocks on a variety of substrates, potentially enabling far-reaching advances in lightweight display, mobile computing, and information storage applications.
159 citations
TL;DR: The implementation of three dimensionally cross-linked, organic nanodielectric multilayers as ultrathin gate dielectrics for a type of thin film transistor device that uses networks of single-walled carbon nanotubes as effective semiconductor thin films suggests that organic dielectric of this general type could provide a promising path to SWNT-based thin film electronics.
Abstract: We report the implementation of three dimensionally cross-linked, organic nanodielectric multilayers as ultrathin gate dielectrics for a type of thin film transistor device that uses networks of single-walled carbon nanotubes as effective semiconductor thin films. Unipolar n- and p-channel devices are demonstrated by use of polymer coatings to control the behavior of the networks. Monolithically integrating these devices yields complementary logic gates. The organic multilayers provide exceptionally good gate dielectrics for these systems and allow for low voltage, low hysteresis operation. The excellent performance characteristics suggest that organic dielectrics of this general type could provide a promising path to SWNT-based thin film electronics.
TL;DR: In this article, the metal/semiconductor contact is modeled as a transmission line, leading to the development of equations analogous to those used for planar contacts, and the advantages and disadvantages of various test structures are discussed.
Abstract: Ohmic contacts to semiconductor nanowires are essential components of many new nanoscale electronic devices. Equations for extracting specific contact resistance (or contact resistivity) from several different test structures have been developed by modeling the metal/semiconductor contact as a transmission line, leading to the development of equations analogous to those used for planar contacts. The advantages and disadvantages of various test structures are discussed. To fabricate test structures using a convenient four-point approach, silicon nanowires have been aligned using field-assisted assembly and contacts fabricated. Finally, specific contact resistances near 5 × 10−4 Ω cm2 have been measured for Ti/Au contacts to p-type Si nanowires with diameters of 78 and 104 nm.
01 Jan 2005
TL;DR: The opportunities and challenges of III-V nanoelectronics for future high-speed, low- power digital logic applications are highlighted and many significant challenges remain to be overcome.
Abstract: This paper highlights the opportunities and challenges of III-V nanoelectronics for future high-speed, low- power digital logic applications. III-V materials in general have significantly higher electron mobility than Si and can potentially play a major role along with Si in future high-speed, low-power computing. The major potential advantage of using a III-V quantum-well field-effect transistor as a logic transistor is that it can be operated under very low supply voltage (e.g., 0.5 V), and hence, lower power dissipation while still achieving very high speed. Compared to other emerging high-mobility materials, such as, carbon nanotubes and semiconductor nanowires, which require "bottom-up" chemical synthesis for formation and suffer from the fundamental placement problem, III-V materials are far more practical in terms of patterning. However, many significant challenges remain to be overcome before III-V materials become applicable for future high-speed, low-power logic applications. These include: (i) finding a compatible high-K gate dielectric on III-Vs, (ii) demonstrating gate length scalability below 35 nm with acceptable I/sub ON//I/sub OFF/ ratio, (iii) improving the hole mobility in III-Vs or finding the right p-channel FET for the complementary metal-oxide-semiconductor (CMOS) configuration, and (iv) integrating III-V materials onto the Si substrate.
TL;DR: In this article, the authors report experimental evidence for superconductivity breakdown in ultranarrow quasi-1D aluminum nanowires, showing that a superconducting nanowire is no longer a superconductor in a sense that it acquires a finite resistance even at temperatures close to absolute zero.
Abstract: Below a certain temperature Tc (typically cryogenic), some materials lose their electric resistance R entering a superconducting state. Following the general trend toward a large scale integration of a greater number of electronic components, it is desirable to use superconducting elements in order to minimize heat dissipation. It is expected that the basic property of a superconductor, i.e., dissipationless electric current, will be preserved at reduced scales required by modern nanoelectronics. Unfortunately, there are indications that for a certain critical size limit of the order of ∼10 nm, below which a “superconducting” nanowire is no longer a superconductor in a sense that it acquires a finite resistance even at temperatures close to absolute zero. In the present paper we report experimental evidence for a superconductivity breakdown in ultranarrow quasi-1D aluminum nanowires.
Book•
01 Jan 2005TL;DR: Superlattice to Nanoelectronics, Second Edition as discussed by the authors, traces the history of the development of superlattices and quantum wells from their origins in 1969, including resonant tunneling via man-made quantum well states, optical properties and Raman scattering in manmade quantum systems, dielectric function and doping of a super-attice; and quantum step and activation energy.
Abstract: Superlattice to Nanoelectronics, Second Edition, traces the history of the development of superlattices and quantum wells from their origins in 1969. Topics discussed include the birth of the superlattice; resonant tunneling via man-made quantum well states; optical properties and Raman scattering in man-made quantum systems; dielectric function and doping of a superlattice; and quantum step and activation energy. The book also covers semiconductor atomic superlattice; Si quantum dots fabricated from annealing amorphous silicon; capacitance, dielectric constant, and doping quantum dots; porous silicon; and quantum impedance of electrons. * Written by one of the founders of this field* Delivers over 20% new material, including new research and new technological applications* Provides a basic understanding of the physics involved from first principles, while adding new depth, using basic mathematics and an explanation of the background essentials
TL;DR: In this article, the scaling of Si CMOS in the sub-65nm regime has been studied and new device structures and new materials have to be created in order to continue the historic progress in information processing and transmission.
TL;DR: In this paper, the authors review advances made in the usage of self-assembly for packaging and potential directions that growth in this area can assume, and conclude with an example of a nanoscale biosensor which directly incorporates the concept of its package into its fabrication process.
Abstract: The packaging of microelectromechanical systems (MEMS) and nanoscale devices constitutes an important area of research and development that is vital to the commercialization of such devices. Packaging needs of these devices include interfaces to nonelectronic domains; integration of structures, devices, and subsystems made with incompatible fabrication processes into a single platform; and the ability to handle a very large numbers of parts. Although serial, robotic assembly methods such as pick-and-place have allowed significant manufacturing feats, self-assembly is an attractive option to tackle packaging issues as the size of individual parts decreases below 300 /spl mu/m. In this paper, we review advances made in the usage of self-assembly for packaging and potential directions that growth in this area can assume. In the micrometer scale, we review the use of capillary forces, gravity, shape recognition, and electric fields to guide two- and three-dimensional self-assembly processes. In the nanoscale, we survey the usage of self-assembled molecular monolayers to solve current packaging issues, DNA hybridization for guiding self-assembly processes of nanoscale devices, and methods used to package nanowires or nanotubes into electronic circuits. We conclude with an example of a nanoscale biosensor which directly incorporates the concept of its package into its fabrication process. Even though the idea of a fully self-packaging system has not been demonstrated to date, the body of work reviewed and discussed here presents a solid foundation for the pursuit of this goal.
31 May 2005
TL;DR: An overview of FinFET technology is presented and how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs is described.
Abstract: Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45nm CMOS technologies. Nonclassical transistor structures such as the FinFET are likely necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs.
TL;DR: In this paper, a bridging technique that connects a large number of highly directional metal-catalyzed nanowires between pre-fabricated electrodes and extends the technique to an electrically isolated structure that allows conduction through the wires to be measured is presented.
Abstract: This paper reviews a novel bridging technique that connects a large number of highly directional metal-catalyzed nanowires between pre-fabricated electrodes and extends the technique to an electrically isolated structure that allows conduction through the nanowires to be measured. Two opposing vertical and electrically isolated semiconductor surfaces are fabricated using coarse optical lithography, along with wet and dry etching. Lateral nanowires are then grown from one surface by metal-catalyst-assisted chemical vapor deposition; nanowires connect to the other vertical surface during growth, forming mechanically robust ‘nanobridges’. By forming the structure on a silicon-on-insulator substrate, electrical isolation is achieved. Electrical measurements indicate that dopant added during nanowire growth is electrically active and of the same magnitude as in planar epitaxial layers.
TL;DR: In this paper, the authors modified the lithography-based technique for cutting nanostructures to efficiently produce solutions of individual nanotubes with average lengths as small as 50 nm.
Abstract: The length of carbon nanotubes has a dramatic impact on their electron transport properties. Transport through short (<300 nm) nanotubes is free of acoustic phonon scattering and thus favours ballistic transport, which is highly desirable for memory and logic devices. Production of uniformly short and pristine nanotubes can lead to high-performance nanotube electronics. We have modified the lithography-based technique for cutting nanostructures to efficiently produce solutions of individual nanotubes with average lengths as small as 50 nm. The formation of uniform aqueous films of singly dispersed nanotubes flanked by top and bottom silicon dioxide layers on patternable substrates allows protection of the sidewalls of the nanotubes. Upon plasma etching the cut nanotubes are recovered by water rinsing of the substrates. This method does not alter the optical absorption of the nanotubes, indicating the preservation of their intrinsic properties. This technology offers an affordable alternative to produce bulk quantities of short, singly dispersed and pristine nanotubes for a vast number of applications other than nanoelectronics.
TL;DR: In this article, the authors report an experimental evidence for a superconductivity breakdown in ultranarrow quasi-1D aluminum nanowires, showing that the material is no longer a superconductor even at temperatures close to absolute zero.
Abstract: Below a certain temperature Tc (typically cryogenic), some materials lose their electric resistance R entering a superconducting state. Folowing the general trend toward a large scale integration of a greater number of electronic components, it is desirable to use superconducting elements in order to minimize heat dissipation. It is expected that the basic property of a superconductor, i.e. dissipationless electric current, will be preserved at reduced scales required by modern nanoelectronics. Unfortunately, there are indications that for a certain critical size limit of the order of 10 nm, below which a "superconducting" wire is no longer a superconductor in a sense that it acquires a finite resistance even at temperatures close to absolute zero. In the present paper we report an experimental evidence for a superconductivity breakdown in ultranarrow quasi-1D aluminum nanowires.
TL;DR: In this article, the feasibility of triple-gate MOSFETs for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area.
Abstract: The feasibility of triple-gate MOSFETs (TGFETs) for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area. Three-dimensional numerical simulations of TGFETs reveal that much more stringent body scaling for SCE control is needed for undoped bodies relative to doped ones (which are not viable for nanoscale devices) due to the suppression of corner current conduction (which is technologically advantageous) in the former. When the undoped body is scaled for adequate SCE control, further analysis shows that the generic TGFET suffers from severe layout-area inefficiency relative to the fully depleted single-gate SOI MOSFET (FDFET) and the double-gate (DG) FinFET, and the inefficiency can be improved only by evolving the TGFET into a virtual FDFET or a virtual DG FinFET. We suggest then that the TGFET is not a feasible nanoscale CMOS transistor, and thus the DG FinFET, which is more scalable than the FDFET, seems to be the most promising candidate for future CMOS applications.
TL;DR: Higher-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) showed that the alloyed ternary CdS(1-x)Se(x) nanowires are highly crystalline, and no phase-separated Cd was observed in these nanowsires.
Abstract: Alloyed ternary CdS1-xSex nanowires were synthesized by template-assisted electrodeposition, in which the ratio of S to Se in the nanowires was controlled by adjusting the relative amounts of the starting materials. Higher-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) showed that the alloyed ternary CdS1-xSex nanowires are highly crystalline, and no phase-separated Cd was observed in these nanowires. Optical measurements indicated that the band-gap engineering can be realized in these CdS1-xSex nanowires through modulating the composition of S and Se. With broadly tunable optical and electrical properties, these alloyed nanowires could be used in color-tuned nanolasers, biological labels, and nanoelectronics.
26 Sep 2005
TL;DR: The spin metal-oxide-semiconductor field effect transistors (spin MOSFETs) as mentioned in this paper are a class of spin transistors that can exhibit significant magnetotransport effects such as large magnetocurrent, and satisfy important requirements for integrated-circuit applications such as high transconductance, low power-delay product, and low off-current.
Abstract: The paper describes a new class of spin transistors referred to as spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs). The fundamental and feasible device structures and the theoretically predicted device performance are presented. The spin MOSFETs not only can exhibit significant magnetotransport effects such as large magnetocurrent, but also can satisfy important requirements for integrated-circuit applications such as high transconductance, low power-delay product, and low off-current. In particular, the additional spin-related degree of freedom in controlling output currents makes the spin MOSFETs attractive building blocks for a nonvolatile memory cell and reconfigurable logic gates on spin-electronic integrated circuits.
TL;DR: In this paper, a self-consistent matrix Green's function method was proposed for modeling single-molecule electronics and a simple conceptual picture for interpreting the results of numerical computation was presented.
Abstract: Exploring the use of individual molecules as active components in electronic devices has been at the forefront of nanoelectronics research in recent years. Compared to semiconductor microelectronics, modeling transport in single-molecule devices is much more difficult due to the necessity of including the effects of the device electronic structure and the interface to the external contacts at the microscopic level. Theoretical formulation of the problem therefore requires integrating the knowledge base in surface science, electronic structure theory, quantum transport, and device modeling into a single unified framework starting from the first principles. In this article, we introduce the theoretical framework for modeling single-molecule electronics and present a simple conceptual picture for interpreting the results of numerical computation. We model the device using a self-consistent matrix Green's function method that combines nonequilibrium Green's function theory of quantum transport with atomic-scale description of the device's electronic structure. We view the single-molecule device as “heterostructures” composed of chemically well-defined atomic groups, and analyze the device characteristics in terms of the charge and potential response of these atomic groups to perturbation induced by the metal–molecule coupling and the applied bias voltage. We demonstrate the power of this approach using as examples devices formed by attaching benzene-based molecules of different size and internal structure to the gold electrodes through sulfur end atoms. © 2005 Wiley Periodicals, Inc. Int J Quantum Chem, 2005
TL;DR: In this paper, the authors show that electron mean-free path in carbon nanotubes can be as large as several micrometers for small bias voltages, for large biases electrons get backscattered by optical and zone-boundary phonons and nanotube resistance can increase by more than 100 times.
Abstract: While electron mean-free path in carbon nanotubes can be as large as several micrometers for small bias voltages, for large biases electrons get backscattered by optical and zone-boundary phonons and nanotube resistance can increase by more than 100 times. This letter reveals this kind of backscattering has a small impact (error <25%) in most interconnect applications of carbon nanotubes in which adequate numbers of nanotubes are connected in parallel. This is mainly due to relatively small electric fields along nanotubes when they are used as interconnects. This is in sharp contrast with transistor applications of carbon nanotubes in which transconductance degrades considerably by electron-phonon scatterings unless their channels are made ultrashort (/spl sim/10 nm).
TL;DR: In this paper, the authors describe a scheme to produce arrays of conductive strips with pitch in the nanometre length scale (NLS) without the use of electron- or ion-beam lithography.
TL;DR: The integration of a complex biological system and a nanoelectronic device is reported, demonstrating that both components retain their functionality while interacting with each other.
Abstract: We report the integration of a complex biological system and a nanoelectronic device, demonstrating that both components retain their functionality while interacting with each other. As the biological system, we use the cell membrane of Halobacterium salinarum. As the nanoelectronic device, we use a nanotube network transistor, which incorporates many individual nanotubes in such a way that entire patches of cell membrane are contacted by nanotubes. We demonstrate that the biophysical properties of the membrane are preserved, that the nanoelectronic devices still function as transistors, and that the two systems interact. Further, we use the interaction to study the charge distribution in the biological system, finding that the electric dipole of the membrane protein bacteriorhodopsin is located 2/3 of the way from the extracellular to the cytoplasmic side.
05 Dec 2005
TL;DR: In this paper, performance limits of n- and p- MOSFETs with Si, Ge, GaAs and InAs channel materials were investigated using a 20 band sp3d5s*-SO semi-empirical atomistic tight-binding model and a top-of-the-barrier seminumerical ballistic transport model.
Abstract: Performance limits of unstrained n- and p- MOSFETs with Si, Ge, GaAs and InAs channel materials are investigated using a 20 band sp3d5s*-SO semi-empirical atomistic tight-binding model and a top-of-the-barrier seminumerical ballistic transport model. It is observed that although the deeply scaled III-V devices offer very high electron injection velocities, their very low conduction band density-of-states strongly degrades their performance. Due to the high density-of-states for both electrons and holes in Ge, nanoscale devices with Ge as channel material are found to outperform all other materials considered