Showing papers by "Soitec published in 2014"

Wafer bonded four-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cells with 44.7% efficiency

Abstract: Triple-junction solar cells from III–V compound semiconductors have thus far delivered the highest solar-electric conversion efficiencies. Increasing the number of junctions generally offers the potential to reach even higher efficiencies, but material quality and the choice of bandgap energies turn out to be even more importance than the number of junctions. Several four-junction solar cell architectures with optimum bandgap combination are found for lattice-mismatched III–V semiconductors as high bandgap materials predominantly possess smaller lattice constant than low bandgap materials. Direct wafer bonding offers a new opportunity to combine such mismatched materials through a permanent, electrically conductive and optically transparent interface. In this work, a GaAs-based top tandem solar cell structure was bonded to an InP-based bottom tandem cell with a difference in lattice constant of 3.7%. The result is a GaInP/GaAs//GaInAsP/GaInAs four-junction solar cell with a new record efficiency of 44.7% at 297-times concentration of the AM1.5d (ASTM G173-03) spectrum. This work demonstrates a successful pathway for reaching highest conversion efficiencies with III–V multi-junction solar cells having four and in the future even more junctions. Copyright © 2014 John Wiley & Sons, Ltd.

Highly uniform and low-loss passive silicon photonics devices using a 300mm CMOS platform

Abstract: Using an advanced 300mm CMOS-platform, we report record-low and highly-uniform propagation loss: 0.45±0.12dB/cm for wires, and 2dB/cm for slot waveguides. For WDM devices, we demonstrate channel variation(3-σ) within-wafer and within-device of 6.1nm and 1.2nm respectively.

Power-Dependent Raman Analysis of Highly Strained Si Nanobridges

Abstract: Strain analysis of complex three-dimensional nanobridges conducted via Raman spectroscopy requires careful experimentation and data analysis supported by simulations. A method combining micro-Raman spectroscopy with finite element analysis is presented, enabling a detailed understanding of strain-sensitive Raman data measured on Si nanobridges. Power-dependent measurements are required to account for the a priori unknown scattering efficiency related to size and geometry. The experimental data is used to assess the validity of previously published phonon deformation potentials.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

Abstract: We report FDSOI devices with a 20nm gate length (L G ) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V dd of 0.75V, competitive effective current (I eff ) reaches 550/340 µA/µm for NFET, at I off of 100/1 nA/µm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V dd of 0.75V, PFET I eff reaches 495/260 µA/µm, at I off of 100/1 nA/µm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.

Surface self-diffusion of silicon during high temperature annealing

Abstract: The atomic-scale mechanisms driving thermally activated self-diffusion on silicon surfaces are investigated by atomic force microscopy. The evolution of surface topography is quantified over a large spatial bandwidth by means of the Power Spectral Density functions. We propose a parametric model, based on the Mullins-Herring (M-H) diffusion equation, to describe the evolution of the surface topography of silicon during thermal annealing. Usually, a stochastic term is introduced into the M-H model in order to describe intrinsic random fluctuations of the system. In this work, we add two stochastic terms describing the surface thermal fluctuations and the oxidation-evaporation phenomenon. Using this extended model, surface evolution during thermal annealing in reducing atmosphere can be predicted for temperatures above the roughening transition. A very good agreement between experimental and theoretical data describing roughness evolution and self-diffusion phenomenon is obtained. The physical origin and time-evolution of these stochastic terms are discussed. Finally, using this model, we explore the limitations of the smoothening of the silicon surfaces by rapid thermal annealing.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

Abstract: Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (∼3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.

Development of high efficiency wafer bonded 4-junction solar cells for concentrator photovoltaic applications

Abstract: The next generation of multi-junction concentrator solar cells will have to reach higher efficiencies than today's devices. At the same time these solar cells must be reliable in the field, be manufacturable with good yield and at sufficiently low cost. Inevitably the request of higher efficiency requires four or even more junction devices. A four-junction solar cell combination of GaInP/GaAs//GaInAsP/GaInAs with bandgap energies of 1.9, 1.4, 1.1, 0.7 eV is developed in a close collaboration between the Fraunhofer ISE, Soitec, CEA-LETI and HZB. This 4-junction cell hits close to the optimum of theoretical efficiency contour plots and has the potential to reach efficiencies up to 50 % under concentration. Challenges are associated with lattice-mismatch between GaAs and InP which is overcome by direct wafer-bonding. The high cost of the InP is addressed by the use of engineered substrates which only require a 500 nm thin mono-crystalline InP layer instead of several hundred µm. Excellent solar cell results up to 44.7 % efficiency have been obtained under concentration for devices manufactured on InP bulk substrates. The high cell efficiency is also supported by out-door characterization of one cell below a Fresnel lens with 16 cm2 aperture area. 38.5 % conversion efficiency has been measured for this mono-module in Freiburg under real operating conditions without any corrections.

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

Abstract: We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.

Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length

Abstract: We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NWs (gate length L G =15 nm) with +90% I ON current improvement.

Reliability of ultra-thin buried oxides for multi-VT FDSOI technology

Abstract: This paper investigates the intrinsic reliability of ultra-thin buried oxides (UTBOX) integrated in the last generation of FDSOI wafers obtained by the Smart Cut™ technology. In term of breakdown reliability, these state-of-the-art UTBOX oxides exhibit comparable performances with thermally-grown SiO 2 references. In “the worst case condition”, the voltage for a 10 years lifetime of 25 nm thick BOX, is estimated to 14 V, which largely exceeds the maximum operating conditions for back-bias [+3 V, –3 V] in advanced FDSOI integrated circuits. This makes UTBOX family of engineered substrates fully compatible and suitable for multi- V T applications.

Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (−2 GPa): From fabrication (Ge enrichment process) to in-depth characterizations

Abstract: 300 mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5 nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as the channel of advanced Fully Depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET). We present in the first part the successful fabrication of 5 nm SGOI wafers. Various characterization techniques are used to investigate the Ge profile and the final strain in the fabricated 5 nm Si 0.7 Ge 0.3 film. Secondary Ions Mass Spectrometry (SIMS) and Scanning Transmission Electron Microscopy (STEM) clearly show that the Ge content is very homogeneous ( x Ge = 30 ± 1%) in the SiGe layer. Raman spectroscopy and High Angle Annular Dark Field (HAADF) STEM both confirm that the 5 nm thick SiGe film is compressively strained (−2 GPa). The second part is dedicated to the sensitivity of the Ge enrichment process (based on numerical modelling). We investigate the impact of single and combined fluctuations of the pre-structure parameters ( T Si , T SiGe,0 , x Ge,0 ) on the final SiGe layer ( T SiGe , x Ge ).

Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm

Abstract: In this work we experimentally demonstrate a novel method to fabricate short channel complementary planar strained Si (sSOI) TFETs with improved tunneling junctions by implantation into silicide method (IIS). For the first time we have successfully fabricated both, n- and p-type TFETs with high on-currents using ultra thin sSOI structures. We demonstrate all Si complementary TFET (C-TFET) inverters with a gain as large as 60 at VDD = 2 V and sharp transitions down to very low VDD = 0.2 V. The first transient response analysis of the NW C-TFET inverter showed a propagation delay of tp

Lithography and doping in strained Si towards atomically precise device fabrication

Abstract: We investigate the ability to introduce strain into atomic-scale silicon device fabrication by performing hydrogen lithography and creating electrically active phosphorus ?-doped silicon on strained silicon-on-insulator (sSOI) substrates. Lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat sSOI(001) surface with a scanning tunnelling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process was investigated allowing us to pattern feature-sizes from several microns down to 1.3?nm. In parallel we have investigated the impact of strain on the electrical properties of P:Si ?-doped layers. Despite the presence of strain inducing surface variations in the silicon substrate we still achieve high carrier densities (>1.0 ? 1014?cm?2) with mobilities of ?100?cm2?V?1?s?1. These results open up the possibility of a scanning-probe lithography approach to the fabrication of strained atomic-scale devices in silicon.

Strained silicon based complementary tunnel-FETs: Steep slope switches for energy efficient electronics

Abstract: Electrical characteristics of silicon nanowire tunnel field effect transistors (TFETs) are presented and benchmarked versus other concepts. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the functional core of the device. Dopant segregation from ion implanted ultrathin silicide contacts is proved as a viable method to achieve steep tunneling junctions. This reduces defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method is applied to strained silicon, specifically to nanowire array transistors, enabling the realization of n-type and p-type TFETs with fairly high currents and complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Gate-all-around Si nanowire array p-type TFETs have been fabricated to demonstrate the impact of electrostatic control on the device performance. A high on-current of 78 μA/μm at VD = VG = 1.1 V is obtained.

Semiconductor structures having active regions comprising InGaN, methods of forming such semiconductor structures, and light emitting devices formed from such semiconductor structures

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

SOI FinFET versus bulk FinFET for 10nm and below

Abstract: FinFETs may in principle be built on either bulk [1–3] or SOI [4–5] substrates. In this paper we will review some of the technical issues associated with choice of substrate, directly comparing empirical results on 10nm hardware for which all the other processes are as much the same as possible. Furthermore, we will discuss the challenges beyond the 10nm generation, where fundamental changes in materials may render the debate moot. Our conclusion and prognosis is that SOI was, is, and will continue to be the technically superior choice.

Heteroepitaxial growth on thin sheets and bulk material: exploring differences in strain relaxation via low-energy electron microscopy

Abstract: Extremely thin single-crystal sheets have unique mechanical properties, which may influence the generation and behaviour of extended defects during heteroepitaxial growth. Using low-energy electron microscopy (LEEM) we investigate the earliest stages of inelastic strain relaxation in SiGe grown heteroepitaxially on Si-on-insulator (SOI) at a sensitivity not possible with other methods, employing a structure that forces dislocations, if they can form at all, to reside at the Si/oxide interface of SOI(0 0 1). LEEM confirms a lower dislocation line energy at the Si/amorphous oxide (SiO2) interface than at the crystalline SiGe/Si interface. The line energy is, however, nonzero, in contrast with earlier assumptions. The lower line energy makes the thermodynamic critical thickness for growth on SOI(0 0 1) lower than on bulk Si(0 0 1) for otherwise identical growth conditions. Nevertheless we can grow heteroepitaxial SiGe films on SOI(0 0 1) that are much thicker than even the thermodynamic critical thickness for growth on bulk Si(0 0 1), suggesting high kinetic barriers for dislocation formation or motion.

Photoactive devices having low bandgap active layers configured for improved efficiency and related methods

Abstract: Photoactive devices include an active region disposed between first and second electrodes and is configured to absorb radiation and generate a voltage between the electrodes. The active region includes an active layer comprising a semiconductor material exhibiting a relatively low bandgap. The active layer has a front surface through which radiation enters the active layer and a relatively rougher back surface on an opposing side of the active layer. Methods of fabricating photoactive devices include the formation of such an active region and electrodes.

Tunnel-FET inverters for ultra-low power logic with supply voltage down to V DD = 0.2 V

Abstract: Complementary MOSFET and Tunnel-FET inverters based on tri-gated strained Si nanowire arrays are demonstrated. The voltage transfer characteristics as well as the inverter supply currents of both inverter types are analyzed and compared. A degradation of the inverter output voltage is observed due to the ambipolar TFET characteristics. Emulated TFET inverters based on the measured transfer characteristics of SiGe/Si heterostructure nanowire array n-channel TFETs with reduced ambipolarity demonstrate inverter switching for supply voltages down to V DD = 0.2 V.

Methods of forming semiconductor structures including iii-v semiconductor material using substrates comprising molybdenum, and structures formed by such methods

Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.

Multiple transfer assembly process

Abstract: This disclosure is related to a manufacturing method for a plurality of photovoltaic cells comprising the steps of: obtaining a plurality of photovoltaic cells placed at a first distance from each other; attaching a stretching material to the plurality of photovoltaic cells; and stretching the stretching material such that the plurality of photovoltaic cells result at a second distance from each other, wherein the second distance is greater that the first distance.

Qualification management to reduce workload variability in semiconductor manufacturing

Abstract: Variability is an inherent component of all production systems. To prevent variability propagation through the whole production line, variability must be constantly monitored, especially for bottleneck toolsets. In this paper, we propose measures to evaluate workload variability for a toolset configuration. Using industrial data, we show how making the toolset configuration more flexible by qualifying products on machines decreases variability. By quantifying the toolset workload variability, our variability measures makes it possible to estimate the variability reduction associated to each new qualification. The industrial results show significant workload variability reduction and capacity improvement.

Photonic curvilinear data processing

Abstract: With more and more photonic data presence in e-beam lithography, the need for efficient and accurate data fracturing is required to meet acceptable manufacturing cycle time. Large photonic based layouts now create high shot count patterns for VSB based tools. Multiple angles, sweeping curves, and non-orthogonal data create a challenge for today’s e-beam tools that are more efficient on Manhattan style data. This paper describes techniques developed and used for creating fractured data for VSB based pattern generators. Proximity Effect Correction is also applied during the fracture process, taking into account variable shot sizes to apply for accuracy and design style. Choosing different fracture routines for pattern data on-the-fly allows for fast and efficient processing. Data interpretation is essential for processing curvilinear data as to its size, angle, and complexity. Fracturing complex angled data into "efficient" shot counts is no longer practical as shot creation now requires knowledge of the actual data content as seen in photonic based pattern data. Simulation and physical printing results prove the implementations for accuracy and write times compared to traditional VSB writing strategies on photonic data. Geometry tolerance is used as part of the fracturing algorithm for controlling edge placement accuracy and tuning to different e-beam processing parameters.

High mobility w-gate nanowire P-FET on cSGOI substrates obtained by Ge enrichment technique

Abstract: Ω-gate nanowires (NW) P-FETs on compressively-strained-SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (L G =15nm and W NW =25nm) with an outstanding I ON current (I ON =860µA/µm at I OFF =140nA/µm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si 0.8 Ge 0.2 -channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for L G =30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at L G =15nm.

Advanced thermally compensated surface acoustic wave device and fabrication method

Abstract: The present invention relates to a method of fabrication of a surface acoustic wave device (20) comprising the step (a) of providing a piezoelectric structure (200), the step (b) of providing a dielectric structure, wherein the step (b) comprises a step (b1) of metalizing (S22) the dielectric structure (220, 221), and the method further comprising the step (c) of bonding (S24) the metalized dielectric structure (231) to the piezoelectric structure (200).

Methods of fabricating semiconductor structures including cavities filled with a sacrifical material

Abstract: Methods of forming semiconductor structures comprising one or more cavities (106), which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate (100), providing a sacrificial material (110) within the one or more cavities, bonding a second substrate (120) over the a surface of the first substrate, forming one or more apertures (140) through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

Process, stack and assembly for separating a structure from a substrate by electromagnetic radiation

Abstract: A method for separating a structure from a substrate through electromagnetic irradiations (EI) belonging to a spectral range comprises the steps of a) providing the substrate, b) forming an absorbent separation layer on the substrate, c) forming the structure to be separated on the separation layer, d) exposing the separation layer to the electromagnetic irradiations (EI) via the substrate such that the separation layer breaks down under the effect of the heat stemming from the absorption, the method being notable in that it comprises a step b1) of forming a transparent thermal barrier layer on the separation layer, the exposure period and the thickness of the thermal barrier layer being adapted such that the temperature of the structure to be separated remains below a threshold during the exposure period, beyond which threshold, faults are likely to appear in the structure.

Quantification of the number of Si interstitials formed by hydrogen implantation in silicon using boron marker layers

Abstract: H implantation results in the appearance of tensile out-of-plane strain in the implanted region which evolves during further annealing. V n H m complexes and/or larger platelets, both co-precipitates of vacancies and H atoms, are believed to be responsible for strain generation. However, during H+ implantation, Frenkel pairs i.e., both vacancies and interstitials are generated. Silicon self-interstitials have been rarely detected and thus their possible role in strain generation has been ignored so far. In this work, we demonstrate that Si interstitials are actually present in large measurable quantities in such implanted layers. For this, we have studied by Secondary Ions Mass Spectrometry the diffusion of boron delta layers during annealing at 350 °C, 550 °C and 850 °C after H implantation at 12 keV with a fluence of 1 × 10 16 H + /cm 2 . The Si self-interstitial supersaturations were extracted by comparison with simulations. Frank dislocation loops, i.e., precipitates of Si atoms, were observed by Transmission Electron Microscopy growing by Ostwald ripening during 850 °C annealing. The supersaturation of Si self-interstitials in dynamical equilibrium with these loops was extracted showing consistency with the values found from the diffusion experiments. These results and more generally the role of interstitials in the strain build up are discussed.

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.