Journal ArticleDOI
Characteristics of InAs/GaSb Line-Tunneling FETs With Buried Drain Technique
TLDR
In this article, an N+ doped buried drain is proposed to form a reverse biased p-n junction with the source and effectively cut the leakage current path off, and the InAs/GaSb line-tunneling field effect transistor (LTFET) with this buried drain technique exhibits high ON-state current and low sub-threshold swing (SS) for five decades of current.Abstract:
The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The “cantilever” or “airbridge” structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the $\text{P}\boldsymbol +$ source and effectively cuts the leakage current path off. The InAs $\boldsymbol /$ GaSb LTFETs with this buried drain technique exhibits ${I}_{ \mathrm{\scriptscriptstyle ON}} \boldsymbol / {I}_{ \mathrm{\scriptscriptstyle OFF}} > {10}^{{7}}$ and SS $\boldsymbol /$ dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications.read more
Citations
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Journal ArticleDOI
A Compact Model for Nanowire Tunneling-FETs
TL;DR: In this article , both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field effect transistors (FETs) based on the same surface potential model, which can be easily integrated as a complete model for circuit-level simulations.
Journal ArticleDOI
Role of Quasi-Fermi potential in modeling III-V TFETs: InAs as a case study
TL;DR: In this paper , the electron quasi-Fermi potential (eQFP) was taken to depend on biasing conditions, both VDS and VGS, and the interpretation of eQFP correctly predicts the electrostatic potential and the drain-to-source band to band tunneling current.
Journal ArticleDOI
A Non-Quasi-Static Model for Nanowire Gate-All-Around Tunneling Field-Effects-Transistors
TL;DR: In this article , a non-quasi-static (NQS) device model is developed for nanowire gate-all-around (GAA) TFETs, which can predict the transient current and capacitance varied with operation frequency.
Journal ArticleDOI
A Comprehensive Review on the Single Gate, Double Gate, Tri-Gate, and Heterojunction Tunnel FET for Future Generation Devices
Journal ArticleDOI
MoS2/Si Tunnel Diodes Based on Comprehensive Transfer Technique
TL;DR: In this article , a comprehensive transfer technique that can mend up the shortages mentioned above with the aid of the water and the thermal release tape (TRT) is proposed, and the MoS2/Si tunnel diode is experimentally demonstrated and the transferred monolayer MoS 2 film with relatively high crystal quality is confirmed by AFM, SEM, and Raman characterizations.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistor: Capacitance Components and Modeling
TL;DR: In this paper, a numerical simulation study of gate capacitance components in a tunneling field effect transistor (TFET) was performed, showing key differences in the partitioning of gate capacitor between the source and drain as compared with a MOSFET.
Journal ArticleDOI
Short-Channel Effects in Tunnel FETs
Jianzhi Wu,Jie Min,Yuan Taur +2 more
TL;DR: In this article, the authors investigated short-channel effects in double-gate tunnel FETs using an analytic model that includes depletion in the source and showed that the drain bias has a significant effect on the potential profile at the source when the channel length is reduced to below twice the scale length.
Journal ArticleDOI
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps
Saurabh Sant,Kirsten E. Moselund,Davide Cutaia,Heinz Schmid,Mattias Borg,Heike Riel,Andreas Schenk +6 more
TL;DR: In this paper, TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET with the same geometry as the fabricated device discussed in the first part were presented.
Journal ArticleDOI
Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si
TL;DR: In this paper, a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET) was employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current (I}_{ \mathrm{\scriptscriptstyle ON}}/{I}$ ) by restricting tunnel barrier width.
Journal ArticleDOI
A Line Tunneling Field-Effect Transistor Based on Misaligned Core–Shell Gate Architecture in Emerging Nanotube FETs
TL;DR: In this article, a new architecture based on an intentional misalignment between the core and shell gate is presented for the nanotube tunnel field effect transistor (NT-TFET).