Journal ArticleDOI
Simulation-Based Study of Si/Si 0.9 Ge 0.1 /Si Hetero-Channel FinFET for Enhanced Performance in Low-Power Applications
TLDR
In this paper, the performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si0.9Ge0.1) channel region is evaluated using three-dimensional TCAD simulations and benchmarked against a conventional p-Channel Si Fin-FET.Abstract:
The performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si0.9Ge0.1) channel region is evaluated using three-dimensional TCAD simulations and benchmarked against a conventional p-channel Si FinFET. The results show that the hetero-channel design provides for larger ON-state current while maintaining comparable electrostatic integrity as the conventional design due to the valence band offset between Si0.9Ge0.1 and Si. The enhanced performance is achieved with a relatively low Ge mole fraction (10%) in the channel region for ease of manufacture. Therefore, the hetero-channel FinFET is promising for future low-power applications.read more
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Journal ArticleDOI
Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
TL;DR: In this article, the authors compute the band structure and shear deformation potentials of strained Si, Ge, and SiGe alloys, and fit the theoretical results to experimental data on the phonon-limited carrier mobilities in bulk Si and Ge.
Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI
A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
C. Auth,A. Aliyarukunju,M. Asoro,D. Bergstrom,V. Bhagwat,J. Birdsall,N. Bisnik,M. Buehler,V. Chikarmane,G. Ding,Q. Fu,H. Gomez,W. Han,D. Hanken,M. Haran,M. Hattendorf,R. Heussner,H. Hiramatsu,B. Ho,S. Jaloviar,I. Jin,S. Joshi,S. Kirby,S. Kosaraju,H. Kothari,G. Leatherman,K. Lee,J. Leib,A. Madhavan,K. Marla,H. Meyer,T. Mule,C. Parker,S. Parthasarathy,C. Pelto,L. Pipes,I. Post,M. Prince,Abdur Rahman,S. Rajamani,A. Saha,J. Dacuna Santos,M. Sharma,V. Sharma,J. Shin,P. Sinha,P. Smith,M. Sprinkle,A. St. Amour,C. Staus,R. Suri,D. Towner,A. Tripathi,A. Tura,C. Ward,A. Yeoh +55 more
TL;DR: In this article, a 10nm logic technology using 3rd-generation FinFET transistors with self-aligned quad patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local intermediate layers is described for high density, a novel selfaligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced.
Journal ArticleDOI
Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping
Mark J. H. van Dal,Georgios Vellianitis,Blandine Duriez,Gerben Doornbos,C. H. Hsieh,Bi-Hui Lee,Kai-Min Yin,Matthias Passlack,Carlos H. Diaz +8 more
TL;DR: In this article, scaled Ge p-channel FinFETs fabricated on a 300mm Si wafer using the aspect-ratio-trapping technique were reported. But, the performance of the Ge pFET was limited by the fact that the trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current.
Proceedings ArticleDOI
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
Dechao Guo,Gauri Karve,Gen Tsutsui,K-Y Lim,Robert R. Robison,T. Hook,Reinaldo A. Vega,Derrick Liu,Stephen W. Bedell,Shogo Mochizuki,F. Lie,Kerem Akarvardar,Miaomiao Wang,Ruqiang Bao,Sean D. Burns,Victor Chan,Kangguo Cheng,James J. Demarest,Jody A. Fronheiser,Pouya Hashemi,James J. Kelly,James Chingwei Li,Nicolas Loubet,Pietro Montanini,Bhagawan Sahu,Muthumanickam Sankarapandian,Stuart A. Sieg,John R. Sporre,Jay W. Strane,Richard G. Southwick,Neeraj Tripathi,Rajasekhar Venigalla,Junli Wang,Koji Watanabe,Chun Wing Yeung,Dinesh Gupta,Bruce B. Doris,Nelson Felix,Jacob Ajey Poovannummoottil,Hemanth Jagannathan,S. Kanakasabapathy,R. Mo,Vijay Narayanan,D. K. Sadana,P. Oldiges,James H. Stathis,Tenko Yamashita,Vamsi Paruchuri,Matthew E. Colburn,Andreas Knorr,R. Divakaruni,Huiming Bu,Mukesh Khare +52 more
TL;DR: CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.
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