Proceedings ArticleDOI
A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
C. Auth,A. Aliyarukunju,M. Asoro,D. Bergstrom,V. Bhagwat,J. Birdsall,N. Bisnik,M. Buehler,V. Chikarmane,G. Ding,Q. Fu,H. Gomez,W. Han,D. Hanken,M. Haran,M. Hattendorf,R. Heussner,H. Hiramatsu,B. Ho,S. Jaloviar,I. Jin,S. Joshi,S. Kirby,S. Kosaraju,H. Kothari,G. Leatherman,K. Lee,J. Leib,A. Madhavan,K. Marla,H. Meyer,T. Mule,C. Parker,S. Parthasarathy,C. Pelto,L. Pipes,I. Post,M. Prince,Abdur Rahman,S. Rajamani,A. Saha,J. Dacuna Santos,M. Sharma,V. Sharma,J. Shin,P. Sinha,P. Smith,M. Sprinkle,A. St. Amour,C. Staus,R. Suri,D. Towner,A. Tripathi,A. Tura,C. Ward,A. Yeoh +55 more
TLDR
In this article, a 10nm logic technology using 3rd-generation FinFET transistors with self-aligned quad patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local intermediate layers is described for high density, a novel selfaligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced.Abstract:
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack The highest drive currents with the highest cell densities are reported for a 10nm technologyread more
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Journal ArticleDOI
Graphene and two-dimensional materials for silicon technology.
Deji Akinwande,Cedric Huyghebaert,Ching-Hua Wang,Martha I. Serna,Stijn Goossens,Lain-Jong Li,H.-S. Philip Wong,H.-S. Philip Wong,Frank H. L. Koppens,Frank H. L. Koppens +9 more
TL;DR: The opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems are reviewed, and the prospects for computational and non-computational applications are considered.
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Scalable energy-efficient magnetoelectric spin-orbit logic.
Sasikanth Manipatruni,Dmitri E. Nikonov,Lin Chia-Ching,Gosavi Tanay,Huichu Liu,Bhagwati Prasad,Yen Lin Huang,Yen Lin Huang,Everton Bonturim,Ramamoorthy Ramesh,Ramamoorthy Ramesh,Ian A. Young +11 more
TL;DR: A scalable spintronic logic device operating via spin–orbit transduction and magnetoelectric switching and using advanced quantum materials shows non-volatility and improved performance and energy efficiency compared with CMOS devices.
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Promises and prospects of two-dimensional transistors
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Journal ArticleDOI
Metrology for the next generation of semiconductor devices
Ndubuisi G. Orji,Mustafa Badaroglu,Bryan M. Barnes,Carlos Beitia,Benjamin Bunday,Umberto Celano,Regis J. Kline,Mark Neisser,Yaw S. Obeng,András E. Vladár +9 more
TL;DR: In this article, the authors review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches, and describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements.
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A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS
TL;DR: A reconfigurable 4096-neuron, 1M-synapse chip in 10-nm FinFET CMOS is developed to accelerate inference and learning for many classes of spiking neural networks (SNNs) with less than 2% overhead for storing connections.
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