Showing papers on "CMOS published in 2017"

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

Abstract: High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

Broadband image sensor array based on graphene–CMOS integration

Abstract: Integrated circuits based on complementary metal-oxide–semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300–2,000 nm) The demonstrated graphene–CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies Graphene–quantum dots on CMOS sensor offers broadband imaging

A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

Abstract: A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack The highest drive currents with the highest cell densities are reported for a 10nm technology

3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications

Abstract: We report a monolithically integrated 3-D metal-oxide memristor crossbar circuit suitable for analog, and in particular, neuromorphic computing applications. The demonstrated crossbar is based on Pt/Al2O3/TiO2– x /TiN/Pt memristors and consists of a stack of two passive $10\times10$ crossbars with shared middle electrodes. The fabrication process has a low, less than 175 °C, temperature budget and includes a planarization step performed before the deposition of the second crossbar layer. These features greatly improve yield and uniformity of the crosspoint devices and allows for utilizing such a fabrication process for integration with CMOS circuits as well as for stacking of multiple crossbar layers. Furthermore, the integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices’ conductance values within the dynamic range of operation. We believe that the demonstrated work is an important milestone toward the implementation of analog artificial neural networks, specifically, those based on 3-D CMOL circuits.

Pushing the limits of CMOS optical parametric amplifiers with USRN:Si 7 N 3 above the two-photon absorption edge

Abstract: CMOS platforms operating at the telecommunications wavelength either reside within the highly dissipative two-photon regime in silicon-based optical devices, or possess small nonlinearities. Bandgap engineering of non-stoichiometric silicon nitride using state-of-the-art fabrication techniques has led to our development of USRN (ultra-silicon-rich nitride) in the form of Si7N3, that possesses a high Kerr nonlinearity (2.8 × 10−13 cm2 W−1), an order of magnitude larger than that in stoichiometric silicon nitride. Here we experimentally demonstrate high-gain optical parametric amplification using USRN, which is compositionally tailored such that the 1,550 nm wavelength resides above the two-photon absorption edge, while still possessing large nonlinearities. Optical parametric gain of 42.5 dB, as well as cascaded four-wave mixing with gain down to the third idler is observed and attributed to the high photon efficiency achieved through operating above the two-photon absorption edge, representing one of the largest optical parametric gains to date on a CMOS platform. Typical CMOS materials in the telecommunications band suffer from two-photon absorption or possess weak Kerr nonlinearities. Here, Ooiet al. demonstrate 42.5 dB optical parametric amplification in ultra-silicon-rich nitride waveguides, designed to have strong nonlinearities with negligible losses.

A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology.

Abstract: As Moore's law reaches its end, traditional computing technology based on the Von Neumann architecture is facing fundamental limits. Among them is poor energy efficiency. This situation motivates the investigation of different processing information paradigms, such as the use of spiking neural networks (SNNs), which also introduce cognitive characteristics. As applications at very high scale are addressed, the energy dissipation needs to be minimized. This effort starts from the neuron cell. In this context, this paper presents the design of an original artificial neuron, in standard 65 nm CMOS technology with optimized energy efficiency. The neuron circuit response is designed as an approximation of the Morris-Lecar theoretical model. In order to implement the non-linear gating variables, which control the ionic channel currents, transistors operating in deep subthreshold are employed. Two different circuit variants describing the neuron model equations have been developed. The first one features spike characteristics, which correlate well with a biological neuron model. The second one is a simplification of the first, designed to exhibit higher spiking frequencies, targeting large scale bio-inspired information processing applications. The most important feature of the fabricated circuits is the energy efficiency of a few femtojoules per spike, which improves prior state-of-the-art by two to three orders of magnitude. This performance is achieved by minimizing two key parameters: the supply voltage and the related membrane capacitance. Meanwhile, the obtained standby power at a resting output does not exceed tens of picowatts. The two variants were sized to 200 and 35 μm2 with the latter reaching a spiking output frequency of 26 kHz. This performance level could address various contexts, such as highly integrated neuro-processors for robotics, neuroscience or medical applications.

A CMOS Passive LPTV Nonmagnetic Circulator and Its Application in a Full-Duplex Receiver

Abstract: Recently, we demonstrated the first CMOS nonmagnetic nonreciprocal passive circulator based on N-path filters that uses time variance to break reciprocity. Here, the analysis of performance metrics, such as loss, isolation, linearity, and tuning range, is presented in terms of the design parameters. The analysis is verified by the measured performance of a 65-nm CMOS circulator prototype that exhibits 1.7 dB of loss in the transmitter-antenna (TX-ANT) and antenna-receiver (ANT-RX) paths, and has high isolation [TX–RX, up to 50 dB through tuning and 20-dB bandwidth (BW) of 32 MHz] and a tuning range of 610–850 MHz. Through an architectural feature specifically designed to enhance TX linearity, the circulator achieves an in-band TX-ANT input-referred third-order intercept point (IIP3) of +27.5 dBm, nearly two orders of magnitude higher than the ANT-RX IIP3 of +8.7 dBm. The circulator is also integrated with a self-interference-canceling full-duplex (FD) RX featuring an analog baseband (BB) SI canceller. The FD RX achieves 42-dB on-chip SI suppression across the circulator and analog BB domains over a 12-MHz signal BW. In conjunction with digital SI and its input-referred third-order intermodulation (IM3) cancellation, the FD RX demonstrates 85-dB overall SI suppression, enabling an FD link budget of −7-dBm TX average output power and −92-dBm noise floor.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films

Abstract: Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units...

On the Design of Wideband Transformer-Based Fourth Order Matching Networks for ${E}$ -Band Receivers in 28-nm CMOS

Abstract: This paper discusses the design of on-chip transformer-based fourth order filters, suitable for mm-Wave highly sensitive broadband low-noise amplifiers (LNAs) and receivers (RXs) implemented in deep-scaled CMOS. Second order effects due to layout parasitics are analyzed and new design techniques are introduced to further enhance the gain-bandwidth product of this class of filters. The design and measurements of a broadband 28-nm bulk CMOS LNA and a sliding-IF RX tailored for ${E}$ -band (i.e., 71–76-GHz and 81–86-GHz) point-to-point communication links are presented. Leveraging the proposed design methodologies, the ${E}$ -band LNA achieves a figure of merit $\approx 10.5$ -dB better than state-of-the-art designs in the same band and comparable to LNAs at lower frequencies. The RX achieves 30.8-dB conversion gain with ${E}$ -band with wide margin.

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology

Abstract: A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion ratio (SNDR) of 55 dB and a spurious free dynamic range (SFDR) of 66 dB with a 4-GHz input signal, is fabricated in the 28-nm CMOS technology, and dissipates 2.9 W. Eight pipeline sub-ADCs are interleaved to achieve 10-GS/s sample rate, and mismatches between sub-ADCs are calibrated in the background. The pipeline sub-ADCs employ a variety of techniques to lower power, like avoiding a dedicated sample-and-hold amplifier (SHA-less), residue scaling, flash background calibration, dithering and inter-stage gain error background calibration. A push–pull input buffer optimized for high-frequency linearity drives the interleaved sub-ADCs to enable >7-GHz bandwidth. A fast turn-ON bootstrapped switch enables 100-ps sampling. The ADC also includes the ability to randomize the sub-ADC selection pattern to further reduce residual interleaving spurs.

Photon-number-resolving megapixel image sensor at room temperature without avalanche gain

Abstract: In several emerging fields of study such as encryption in optical communications, determination of the number of photons in an optical pulse is of great importance. Typically, such photon-number-resolving sensors require operation at very low temperature (e.g., 4 K for superconducting-based detectors) and are limited to low pixel count (e.g., hundreds). In this paper, a CMOS-based photon-counting image sensor is presented with photon-number-resolving capability that operates at room temperature with resolution of 1 megapixel. Termed a quanta image sensor, the device is implemented in a commercial stacked (3D) backside-illuminated CMOS image sensor process. Without the use of avalanche multiplication, the 1.1 μm pixel-pitch device achieves 0.21e− rms average read noise with average dark count rate per pixel less than 0.2e−/s, and 1040 fps readout rate. This novel platform technology fits the needs of high-speed, high-resolution, and accurate photon-counting imaging for scientific, space, security, and low-light imaging as well as a broader range of other applications.

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

Abstract: This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver. The transceivers are both fabricated in a standard 65-nm CMOS technology. For the proposed one-stream transceiver, the TX-to-RX error vector magnitude (EVM) is less than −23.9 dB for 64-QAM wireless communication in all four channels defined in the IEEE 802.11ad/WiGig. The maximum communication distance with the full rate can reach 0.13 m for 64 QAM, 0.8 m for 16 QAM, and 2.6 m for QPSK using 14-dBi horn antennas. A data rate of 28.16 Gb/s is achieved in 16 QAM by four-channel bonding. The transmitter, receiver, and phase-locked loop consume 186, 155, and 64 mW, respectively. The core area of the transceiver is 3.9 mm2. For the proposed two-stream FI transceiver, four-channel bonding in 64 QAM is realized with a data rate of 42.24 Gb/s and an EVM of less than −23 dB. The front end consumes 544 mW in transmitting mode and 432 mW in receiving mode from a 1.2-V supply. The core area of the transceiver is 7.2 mm2.

Implicit Common-Mode Resonance in LC Oscillators

Abstract: The performance of a differential LC oscillator can be enhanced by resonating the common mode of the circuit at twice the oscillation frequency. When this technique is correctly employed, Q-degradation due to the triode operation of the differential pair is eliminated and flicker noise is nulled. Until recently, one or more tail inductors have been used to achieve this common-mode resonance. In this paper, we demonstrate that additional inductors are not strictly necessary by showing that common-mode resonance can be obtained using a single tank. We present an NMOS architecture that uses a single differential inductor and a CMOS design that uses a single transformer. Prototypes are presented that achieve figure-of-merits of 192 and 195 dBc/Hz, respectively.

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting

Abstract: This brief presents a dual-path CMOS rectifier with adaptive control for ultrahigh-frequency (UHF) RF energy harvesters. The input power range with high power conversion efficiency (high PCE) of the rectifier is extended by the proposed architecture, which includes a low-power path and a high-power path. The dual-path rectifier with an adaptive control circuit is fabricated in a 65-nm CMOS process. Operating at 900 MHz and driving a 147-kΩ load resistor, the measured PCE of this work can be maintained above 20% with an 11-dB input range from -16 to -5 dBm, while only an 8-dB input range can be achieved with traditional single-path rectifiers. A sensitivity of -17.7 dBm is measured with 1-V output voltage across a capacitive load.

Rail-to-Rail-Input Dual-Radio 64-Channel Closed-Loop Neurostimulator

Abstract: A 64-channel 0.13- $\mu \text{m}$ CMOS system on a chip (SoC) for neuroelectrical monitoring and responsive neurostimulation is presented. The $\Delta \Sigma $ -based neural channel records signals with rail-to-rail dc offset at the input without any area-intensive dc-removing passive components, which leads to a compact 0.013-mm2 integration area of recording and stimulation circuits. The channel consumes 630 nW, yields a signal to noise and distortion ratio of 72.2 dB, a 1.13- $\mu $ Vrms integrated input-referred noise over 0.1–500 Hz frequency range, and a noise efficiency factor of 2.86. Analog multipliers are implemented in each channel with minimum additional area cost by reusing the multi-bit current-digital to analog converter that is originally placed for current-mode stimulation. The multipliers are used for compact implementation of bandpass finite impulse response filters, as well as voltage gain scaling. A tri-core low-power DSP conducts phase-synchrony-based neurophysiological event detection and triggers a subset of 64 programmable arbitrary-waveform current-mode stimulators for subsequent neuromodulation. Two ultra-wideband (UWB) wireless transmitters communicate to receivers located at 10 cm to 2 m distance from the implanted SoC with data rates of 10–46 Mb/s, respectively. An inductive link that operates at 1.5 MHz provides power to the SoC and is also used to communicate commands to an on-chip ASK receiver. The chip occupies 6 mm2 while consuming 1.07 and 5.44 mW with delay-based and voltage controlled oscillator-based UWB transmitters, respectively. The SoC is validated in vivo using epilepsy monitoring (seizure detection) and treatment (seizure suppression) experiments.

A 79-GHz 2 $\times $ 2 MIMO PMCW Radar SoC in 28-nm CMOS

Abstract: In this paper, the concept of phase modulated MIMO radars is explained and demonstrated with a 28-nm CMOS fully integrated 79-GHz radar SoC. It includes two transmitters, two receivers, and the mm-wave frequency generation. The receivers’ outputs are digitized by on-chip ADCs and processed by a custom designed digital core, which performs correlation and accumulation with a pseudorandom sequence used in transmission. The SoC consumes 1 W to achieve 7.5 cm range resolution. A module with antennas allows for 5° resolution over ±60° elevation and azimuth scan in 2 $\times $ 2 code domain MIMO operation. A 4 $\times $ 4 MIMO system is also demonstrated by means of two SoCs mounted on the same module.

Monolithic ultrasound fingerprint sensor.

Abstract: This paper presents a 591×438-DPI ultrasonic fingerprint sensor. The sensor is based on a piezoelectric micromachined ultrasonic transducer (PMUT) array that is bonded at wafer-level to complementary metal oxide semiconductor (CMOS) signal processing electronics to produce a pulse-echo ultrasonic imager on a chip. To meet the 500-DPI standard for consumer fingerprint sensors, the PMUT pitch was reduced by approximately a factor of two relative to an earlier design. We conducted a systematic design study of the individual PMUT and array to achieve this scaling while maintaining a high fill-factor. The resulting 110×56-PMUT array, composed of 30×43-μm2 rectangular PMUTs, achieved a 51.7% fill-factor, three times greater than that of the previous design. Together with the custom CMOS ASIC, the sensor achieves 2 mV kPa-1 sensitivity, 15 kPa pressure output, 75 μm lateral resolution, and 150 μm axial resolution in a 4.6 mm×3.2 mm image. To the best of our knowledge, we have demonstrated the first MEMS ultrasonic fingerprint sensor capable of imaging epidermis and sub-surface layer fingerprints.

Homogeneous 2D MoTe2 p–n Junctions and CMOS Inverters formed by Atomic-Layer-Deposition-Induced Doping

Abstract: Recently, α-MoTe2 , a 2D transition-metal dichalcogenide (TMD), has shown outstanding properties, aiming at future electronic devices. Such TMD structures without surface dangling bonds make the 2D α-MoTe2 a more favorable candidate than conventional 3D Si on the scale of a few nanometers. The bandgap of thin α-MoTe2 appears close to that of Si and is quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control the charge-carrier polarity of MoTe2 , functional devices such as p-n junction or complementary metal-oxide-semiconductor (CMOS) inverters have not been reported. Here, we demonstrate a 2D CMOS inverter and p-n junction diode in a single α-MoTe2 nanosheet by a straightforward selective doping technique. In a single α-MoTe2 flake, an initially p-doped channel is selectively converted to an n-doped region with high electron mobility of 18 cm2 V-1 s-1 by atomic-layer-deposition-induced H-doping. The ultrathin CMOS inverter exhibits a high DC voltage gain of 29, an AC gain of 18 at 1 kHz, and a low static power consumption of a few nanowatts. The results show a great potential of α-MoTe2 for future electronic devices based on 2D semiconducting materials.

A Fully Integrated Reconfigurable Self-Startup RF Energy-Harvesting System With Storage Capability

Abstract: This paper introduces a fully integrated RF energy-harvesting system. The system can simultaneously deliver the current demanded by external dc loads and store the extra energy in external capacitors, during periods of extra output power. The design is fabricated in 0.18-μm CMOS technology, and the active chip area is 1.08 mm 2 . The proposed self-startup system is reconfigurable with an integrated LC matching network, an RF rectifier, and a power management/controller unit, which consumes 66-157 nW. The required clock generation and the voltage reference circuit are integrated on the same chip. Duty cycle control is used to operate for the low input power that cannot provide the demanded output power. Moreover, the number of stages of the RF rectifier is reconfigurable to increase the efficiency of the available output power. For high available power, a secondary path is activated to charge an external energy storage element. The measured RF input power sensitivity is -14.8 dBm at a 1-V dc output.

A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations

Abstract: A complementary noise-canceling CMOS low-noise amplifier (LNA) with enhanced linearity is proposed. An active shunt feedback input stage offers input matching, while extended input matching bandwidth is acquired by a $\pi$ -type matching network. The intrinsic noise cancellation mechanism maintains acceptable noise figure (NF) with reduced power consumption due to the current reuse principle. Multiple complementary nMOS and pMOS configurations commonly restrain nonlinear components in individual stage of the LNA. Complementary multigated transistor architecture is further employed to nullify the third-order distortion of noise-canceling stage and compensate the second-order nonlinearity of that. High third-order input intercept point (IIP3) is thus obtained, while the second-order input intercept point (IIP2) is guaranteed by differential operation. Implemented in a 0.18- $\mu \text{m}$ CMOS process, the experimental results show that the proposed LNA provides a maximum gain of 17.5 dB and an input 1-dB compression point (IP1 dB) of −3 dBm. An NF of 2.9–3.5 dB and an IIP3 of 10.6–14.3 dBm are obtained from 0.1 to 2 GHz, respectively. The circuit core only draws 9.7 mA from a 2.2 V supply.

A 28GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular system

Abstract: This paper describes a 28GHz CMOS direct conversion transceiver with packaged 2×4 patch antenna arrays for 5G communication. Test results show good RF performances of Rx NF 6.7dB, Maximum Tx EIRP 31.5dBm (1PA P out_sat =10.5dBm), LO integrated phase noise −37.8dBc (0.67°), Rx/Tx EVM around 2.2% (−33.1dB) at mid RF power, and well-fitted beam control capability.

A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing

Abstract: Demand for highly energy-efficient coprocessor for the inference computation of deep neural networks is increasing. We propose the time-domain neural network (TDNN), which employs time-domain analog and digital mixed-signal processing (TDAMS) that uses delay time as the analog signal. TDNN not only exploits energy-efficient analog computing, but also enables fully spatially unrolled architecture by the hardware-efficient feature of TDAMS. The proposed fully spatially unrolled architecture reduces energy-hungry data moving for weight and activations, thus contributing to significant improvement of energy efficiency. We also propose useful training techniques that mitigate the non-ideal effect of analog circuits, which enables to simplify the circuits and leads to maximizing the energy efficiency. The proof-of-concept chip shows unprecedentedly high energy efficiency of 48.2 TSop/s/W.

A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Abstract: We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F2 digital power amplifier (PA), featuring high efficiency. Low 1/ $f$ DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (~10 Gsamples/s) with intermediate frequency placed beyond 1/ $f$ noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE.

KiloCore: A 32-nm 1000-Processor Computational Array

Abstract: A processor array containing 1000 independent processors and 12 memory modules was fabricated in 32-nm partially depleted silicon on insulator CMOS. The programmable processors occupy 0.055 mm2 each, contain no algorithm-specific hardware, and operate up to an average maximum clock frequency of 1.78 GHz at 1.1 V. At 0.9 V, processors operating at an average of 1.24 GHz dissipate 17 mW while issuing one instruction per cycle. At 0.56 V, processors operating at an average of 115 MHz dissipate 0.61 mW while issuing one instruction per cycle, resulting in an energy consumption of 5.3 pJ/instruction. On-die communication is performed by complementary circuit and packet-based networks that yield a total array bisection bandwidth of 4.2 Tb/s. Independent memory modules handle data and instructions and operate up to an average maximum clock frequency of 1.77 GHz at 1.1 V. All processors, their packet routers, and the memory modules contain unconstrained clock oscillators within independent clock domains that adapt to large supply voltage noise. Compared with a variety of Intel i7s and Nvidia GPUs, the KiloCore at 1.1 V has geometric mean improvements of 4.3 $\times$ higher throughput per area and 9.4 $\times$ higher energy efficiency for AES encryption, 4095-b low-density parity-check decoding, 4096-point complex fast Fourier transform, and 100-B record sorting applications.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

Abstract: Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

Abstract: In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 Vin gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

A 54.4–90 GHz Low-Noise Amplifier in 65-nm CMOS

Abstract: This paper proposes a transformer-based broadband low-noise amplifier (LNA) for millimeter-wave application. The proposed LNA has four common-source stages. Three transformers are used to connect the drains of the former transistors and the sources of the following transistors to boost the transconductances of the following transistors. Thus, the gain of the circuit is effectively increased. In addition, the noise figure (NF) is decreased because the noise contributions of the following stages are further suppressed by the application of the transformers. To enhance the gain bandwidth, the gate inductor in each inter-stage matching network is independently adjusted to separate the main poles of the four stages. The LNA is demonstrated using a commercial 65-nm CMOS process. According to the measurement results, a maximum gain of 17.7 GHz at 67 GHz and a 3-dB gain bandwidth of 35.6 GHz are achieved. The measured NF is 5.4–7.4 dB at 54–67 GHz. The tested input 1-dB gain compression point (IP $_{1\,\text {dB}}$ ) ranges from −15.4 to −11.7 dBm in the entire 3-dB gain bandwidth. With 1-V power supply, the LNA consumes 19-mA dc current. The chip size is only 0.37 mm2 with all pads.

Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial.

Abstract: We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 [Formula: see text] CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are shared among 56 channels resulting in 0.018 [Formula: see text] effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μVrms over the bandwidth of 1 Hz to 1 kHz. The 8.7 [Formula: see text] chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.

A Low-Power Wireless Piezoelectric Sensor-Based Respiration Monitoring System Realized in CMOS Process

Abstract: This paper presents a methodology of monitoring respiration pattern using piezoelectric transducer incorporating CMOS integrated circuits for signal processing and data transmission. As a proof of concept, the system has been tested by placing electrodes on human chest using adhesive hydrogel to detect the pulsatile vibration due to respiration. The system can be used either as a wearable device itself or alternatively can be attached to a jacket or a chest belt. The front-end transducer is a piezoelectric material-based sensor, which is comprised of a ferroelectric polymer named polyvinylidene-fluoride (PVDF). PVDF is also biocompatible, which makes the sensor suitable to be used as a wearable device. The charge produced by the sensor is converted to a proportional voltage signal with the help of a charge amplifier designed in a standard 130-nm CMOS process with eight metal and one poly layer. The analog voltage signal acquired from the charge amplifier is then converted into a digital signal using a reconfigurable pipelined analog-to-digital converter for ease of transmission. An impulse-radio ultra-wideband transmitter operating in the frequency range of 3.1–5 GHz is designed for wireless transmission of the data. The smaller footprint, lighter weight, wireless telemetry, and low-cost material along with the low-power integrated CMOS circuitry for signal processing and data transmission make the proposed system an attractive choice for stable respiration monitoring system.

Stateful Reconfigurable Logic via a Single-Voltage-Gated Spin Hall-Effect Driven Magnetic Tunnel Junction in a Spintronic Memory

Abstract: Stateful in-memory logic (IML) is a promising paradigm to realize the unity of data storage and processing in the same die, exhibiting great feasibility to break the bottleneck of the conventional von Neumann architecture. On the roadmap toward developing such a logic platform, a critical step is the effective and efficient realization of a complete set of logic functions within a memory. In this paper, we report a realization of stateful reconfigurable logic functions via a single three-terminal magnetic tunnel junction (MTJ) device within a spintronic memory by exploiting the novel voltage-gated spin Hall-effect driven magnetization switching mechanism. This proposed reconfigurable IML methodology can be implemented within either a typical memory array or a cross-point array architecture. The feasibility of the proposed approach is successfully demonstrated with hybrid MTJ/CMOS circuit simulations. We believe our work may promote the research and development of the revolutionary IML for future non-von Neumann architectures.