Showing papers on "Strained silicon published in 2017"

A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

Abstract: A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack The highest drive currents with the highest cell densities are reported for a 10nm technology

Graphene Modulators and Switches Integrated on Silicon and Silicon Nitride Waveguide

Abstract: The optoelectronic properties of graphene attracted a lot of interest in recent years. Several demonstrations of integrated graphene based modulators, switches, detectors, and nonlinear devices have been reported. We present here a comprehensive study investigating the different design tradeoffs involved in realizing, in particular, graphene-based modulators and switches. We compare four representative hybrid graphene-waveguide configurations, focusing on optimizing their dimensions, the gate-oxide thickness, the polarization, the operating wavelength, and contact definition. We study both static and dynamic behavior, defining a relevant figure of merit. We find that a 20-μm device based on silicon waveguides should allow for 25-GBit/s modulation rate and an extinction ratio of 5 dB. A 200-μm long SiN device on the other hand should allow for 23-dB extinction ratio and switching speeds down to 0.4 ns.

Low-Absorbing and Thermally Stable Industrial Silicon Nitride Films With Very Low Surface Recombination

Abstract: Amorphous silicon nitride has become the state-of-the-art antireflection coating for silicon solar cells. Optimization of silicon nitride films requires consideration of both the film's optical and electrical properties. It is commonly assumed that silicon-rich silicon nitride films (films with high refractive index) provide better surface passivation, compared to that obtained by films with lower indices. However, silicon-rich films are usually very absorptive in the short (and even medium) wavelength range. Development of low absorption silicon nitride films, that provide good surface passivation, is therefore highly valuable. In this study we compare nine different industrial silicon nitride films, all with similarly low refractive index of 2.09 ± 0.01 measured at 633 nm. We demonstrate that these films exhibit very different electrical, chemical, and optical properties despite their similar refractive index values and correlate these differences with the specific deposition conditions. As a result of this investigation, we have developed industrial thermally stable low-absorbing silicon nitride films that provide excellent surface passivation, with surface saturation current density of 7 fA/cm2 on both n- and p-type wafers. We demonstrate that the developed low absorption films provide surface passivation with equal quality to that obtained by industrial silicon-rich silicon nitride films.

Modulation Doping of Silicon using Aluminium-induced Acceptor States in Silicon Dioxide

Abstract: All electronic, optoelectronic or photovoltaic applications of silicon depend on controlling majority charge carriers via doping with impurity atoms. Nanoscale silicon is omnipresent in fundamental research (quantum dots, nanowires) but also approached in future technology nodes of the microelectronics industry. In general, silicon nanovolumes, irrespective of their intended purpose, suffer from effects that impede conventional doping due to fundamental physical principles such as out-diffusion, statistics of small numbers, quantum- or dielectric confinement. In analogy to the concept of modulation doping, originally invented for III-V semiconductors, we demonstrate a heterostructure modulation doping method for silicon. Our approach utilizes a specific acceptor state of aluminium atoms in silicon dioxide to generate holes as majority carriers in adjacent silicon. By relocating the dopants from silicon to silicon dioxide, Si nanoscale doping problems are circumvented. In addition, the concept of aluminium-induced acceptor states for passivating hole selective tunnelling contacts as required for high-efficiency photovoltaics is presented and corroborated by first carrier lifetime and tunnelling current measurements.

Quasiatomic layer etching of silicon nitride with independent control of directionality and selectivity

Abstract: Atomic layer etching has emerged as a viable approach to address the challenges associated with continuous or quasicontinuous plasma processes. To this end, the authors previously reported the quasiatomic layer etching of silicon nitride via sequential exposure to hydrogen and fluorinated plasma. The underlying premise was the surface modification via implantation of hydrogen ions into silicon nitride resulting in an anisotropic etch. In this paper, the authors will demonstrate that a similar enhancement in reactivity of silicon nitride can also be attained via diffusion of hydrogen atoms into silicon nitride with the resultant etch being isotropic. These results confirm the realization of self-limiting etch of silicon nitride with tunable directionality. Selectivity to oxide is >100 and damage to underlying silicon can be minimized by optimizing the flux of atomic fluorine during the exposure to fluorinated plasma. Thus, hydrogen plasma step controls the directionality while fluorinated plasma step deter...

3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects

Abstract: This paper presents a detailed study of the response of a new structure namely, high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual material bottom gate, towards various short channel effects, namely, drain-induced barrier lowering, threshold voltage roll-off, hot carrier effect and subthreshold swing Based on the 3-D Poisson’s equation, the surface potential of the device is calculated along with its threshold voltage and electric field The impact on the device performance due to the variation of different device parameters is also studied The analytical results are verified using the simulated results obtained from ATLAS, a 3-D device simulator from SILVACO

Optimization of the window layer in large area silicon heterojunction solar cells

Abstract: Silicon heterojunction solar cells have shown great advantage due to their large open-circuit voltage which induces a high energy conversion efficiency. However, the short-circuit current density is limited by the high light absorption of an n-type amorphous silicon window layer in the short-wavelength range. Here an amorphous silicon oxide film was introduced to replace the window layer. The increasing oxygen content in amorphous silicon oxide layers leads to the enlarged optical band gap and the enhanced short-wavelength transmittance. As a result, the short-circuit current density increases obviously which comes from the high transmittance of amorphous silicon oxide films due to the wider band gap. Furthermore, the highly phosphorous-doped amorphous silicon layer was introduced to improve the contact between transparent conductive oxide layer and n-type amorphous silicon oxide layer. The carrier transport property is enhanced and thus the fill factor increases significantly. Finally, a silicon heterojunction solar cell with an area of 238.95 cm2 was prepared, yielding a total-area efficiency up to 21.1%. Overall, the results indicate that amorphous silicon oxide films can be applied to silicon heterojunction solar cells as a window layer, which provides a new route to obtain higher energy conversion efficiency.

Quantum properties of dichroic silicon vacancies in silicon carbide

Abstract: The controlled generation and manipulation of atom-like defects in solids has a wide range of applications in quantum technology. Although various defect centres have displayed promise as either quantum sensors, single photon emitters or light-matter interfaces, the search for an ideal defect with multi-functional ability remains open. In this spirit, we investigate here the optical and spin properties of the V1 defect centre, one of the silicon vacancy defects in the 4H polytype of silicon carbide (SiC). The V1 centre in 4H-SiC features two well-distinguishable sharp optical transitions and a unique S=3/2 electronic spin, which holds promise to implement a robust spin-photon interface. Here, we investigate the V1 defect at low temperatures using optical excitation and magnetic resonance techniques. The measurements, which are performed on ensemble, as well as on single centres, prove that this centre combines coherent optical emission, with up to 40% of the radiation emitted into the zero-phonon line (ZPL), a strong optical spin signal and long spin coherence time. These results single out the V1 defect in SiC as a promising system for spin-based quantum technologies.

On the influence of interface charging dynamics and stressing conditions in strained silicon devices.

Abstract: The performance of strained silicon devices based on the deposition of a top silicon nitride layer with high stress have been thoroughly analyzed by means of simulations and experimental results. Results clearly indicate that the electro-optic static response is basically governed by carrier effects. A first evidence is the appearance of a variable optical absorption with the applied voltage that should not occur in case of having a purely electro-optic Pockels effect. However, hysteresis and saturation effects are also observed. We demonstrate that such effects are mainly due to the carrier trapping dynamics at the interface between the silicon and the silicon nitride and their influence on the silicon nitride charge. This theory is further confirmed by analyzing identical devices but with the silicon nitride cladding layer optimized to have intrinsic stresses of opposite sign and magnitude. The latter is achieved by a post annealing process which produces a defect healing and consequently a reduction of the silicon nitride charge. Raman measurements are also carried out to confirm the obtained results.

Semiconductor device and method of manufacturing the same

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Spin and optical properties of silicon vacancies in silicon carbide (a review)

Abstract: We discuss the fine structure and spin dynamics of spin-3/2 centers associated with silicon vacancies in silicon carbide. The centers have optically addressable spin states which makes them highly promising for quantum technologies. The fine structure of the spin centers turns out to be highly sensitive to mechanical pressure, external magnetic and electric fields, temperature variation, etc., which can be utilized for efficient room-temperature sensing, particularly by purely optical means or through the optically detected magnetic resonance. We discuss the experimental achievements in magnetometry and thermometry based on the spin state mixing at level anticrossings in an external magnetic field and the underlying microscopic mechanisms. We also discuss spin fluctuations in an ensemble of vacancies caused by interaction with environment.

Performance comparison for FinFETs, nanowire and stacked nanowires FETs: Focus on the influence of surface roughness and thermal effects

Abstract: We perform a comprehensive comparison of FinFETs, stacked nanowires (stacked NWs), circular and square gate-all-around (GAA) n-FETs with same footprint, by using an in-house deterministic BTE solver accounting for quantum confinement, a wide set of scattering mechanisms and self-heating. We show that an increase in surface roughness (SR) can frustrate the improvement in on current, I on , that for high-quality interfaces we observe in stacked NWs compared to FinFETs. Simulations suggest that SR also influences whether or not In0.53Ga0.47As can provide better I on than strained silicon (sSi).

Nanowire isolation scheme to reduce parasitic capacitance

Abstract: A method for manufacturing a semiconductor device includes forming a doped silicon layer on a bulk substrate, forming an undoped silicon cap layer on the doped silicon layer, forming a stacked configuration of silicon germanium (SiGe) and silicon layers on the undoped silicon cap layer, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on an SiGe layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, the doped silicon layer and the undoped silicon cap layer, forming a spacer layer on each of the plurality of dummy gates, and on the doped silicon layer and the undoped silicon cap layer, selectively etching the doped silicon layer with respect to the undoped silicon layer, and filling the area from where the doped s silicon layer was selectively removed with a dielectric layer.

Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

Abstract: Two dimensional threshold voltage model of ion-implanted strained-Si double-material double-gate MOSFETs has been done based on the solution of two dimensional Poisson’s equation in the channel region using the parabolic approximation method. Novelty of the proposed device structure lies in the amalgamation of the advantages of both the strained-Si channel and double-material double-gate structure with a vertical Gaussian-like doping profile. The effects of different device parameters (such as device channel length, gate length ratios, germanium mole fraction) and doping parameters (such as projected range, straggle parameter) on threshold voltage of the proposed structure have been investigated. It is observed that the subthreshold performance of the device can be improved by simply controlling the doping parameters while maintaining other device parameters constant. The modeling results show a good agreement with the numerical simulation data obtained by using ATLAS™, a 2D device simulator from SILVACO.

Studying the Influence of n-Type Strained (111) Silicon on the Piezoresistive Coefficients

Abstract: This paper investigates the effect of inducing a pre-strain state into the (111) silicon substrate on the piezoresistive coefficients. For this purpose, a ten-element sensing rosette has been fabricated on strained and unstrained silicon substrates and fully calibrated using uniaxial, thermal, and hydrostatic loading. The strained silicon technique was integrated during the microfabrication process using a highly compressive film produced by plasma enhanced chemical vapor deposition silicon nitride. This layer induces a tensile strain at the front side of the substrate where the sensing elements were fabricated. The calibration results show that the tensile strained silicon has smaller longitudinal and transverse piezoresistive coefficients than those on unstrained silicon. On the other hand, the shear piezoresistive and the pressure coefficients were increased by 23% and 30%, respectively.

Comprehensive description of the electro-optic effects in strained silicon waveguides

Abstract: We present a novel and comprehensive analysis method that considers both the plasma-dispersion effect and the strain-induced Pockels effect to faithfully describe the electro-optic effects taking place in a strained silicon waveguide under an applied voltage. The change in carrier distribution arising from the application of a voltage leads to a redistribution of the electrostatic field which deeply affects the strain-induced Pockels effect. By simulating the strain gradient distribution inside the waveguide together with the free carrier concentration in silicon, we were able to describe that the effective index change due to the Pockels effect in strained silicon waveguides and the applied voltage have a nonlinear relationship.

Solution-based polycrystalline silicon transistors produced on a paper substrate

Abstract: Printing of electronics is pursued as a low-cost alternative to conventional manufacturing processes. In addition, owing to relatively low process temperatures, flexible substrates can be used enabling novel applications. Among flexible substrates, paper was found to be a particularly interesting candidate, since it has an order of magnitude lower price than low-cost polymer alternatives, and is biodegradable. As ink materials, organic and metal-oxide semiconductors are thoroughly being investigated; however, they lack in electric performance compared to silicon in terms of device mobility, reliability, and energy efficiency. In recent years, liquid precursors for silicon were found and used to create polycrystalline silicon (poly-Si). However, fabrication of transistors on top of low-cost flexible substrates such as paper has remained an outstanding challenge. Here we demonstrate both p-channel and n-channel poly-Si thin-film transistors (TFTs) fabricated directly on top of paper with field-effect mobilities of 6.2 and 2.0 cm2/V s, respectively. Many fabrication challenges have been overcome by limiting the maximum process temperature to approximately 100 °C, and avoiding liquid chemicals commonly used for etching and cleaning. Patterning of poly-Si has been achieved by additive selective crystallization of the precursor film using an excimer laser. This work serves as a proof of concept, and has the potential to further improve device performance. Owing to the low-cost, biodegradable nature of paper, and the high performance, reliability, and energy efficiency of poly-Si TFTs, this work opens a pathway toward truly low-cost, low-power, recyclable applications including smart packages, biodegradable health monitoring units, flexible displays, and disposable sensor nodes.

Development of double strained Si channel for heterostructure on insulator MOSFET

Abstract: Strained Silicon Technology is known for its ability to enhance carrier mobility while simultaneously boost MOSFET devices performance. Double strained silicon channel MOSFET with strained silicon-germanium sandwiched in between has been developed, incorporating quantum effects for counter balancing the reduced threshold voltage. A comparison of the conventional strained silicon on relaxed silicon-germanium with the double strained silicon channel MOSFET is perceived. Based on the simulation results, the heterostructure MOS channel has shown superior device characteristics with a small reduction in the threshold voltage by increasing strain in the channel region.

Superior NBTI in High-k SiGe Transistors–Part II: Theory

Abstract: The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

Atom probe tomography of size-controlled phosphorus doped silicon nanocrystals

Abstract: Doping of silicon nanocrystals is essential to control their electronic and optical properties. The incorporation of an impurity into a silicon nanovolume is a nontrivial task due to the self-purification effect. Here, a systematic atom probe tomography study of the phosphorus distribution and incorporation in size-controlled silicon nanocrystals embedded in silicon dioxide is presented. Qualitatively, it turns out that the phosphorus distribution in the system follows a universal, nanocrystal-size independent trend: phosphorus-enrichment at the interface with a substantial phosphorus-incorporation in the silicon nanocrystal as small as 2 nm in diameter. This clearly contradicts strict self-purification. These observations are explained by the bulk-solubility and -segregation behaviour, kinetic effects related to the diffusion lengths, and nanoscale interface strain. The quantitative determination of the amount of phosphorus atoms per quantum dot enables a systematic understanding of phosphorus-induced effects on optical and electronic properties of silicon nanovolumes.

Electronic Quality Improvement of Highly Defective Quasi-Mono Silicon Material by Phosphorus Diffusion Gettering

Abstract: Quasi-mono silicon (QM-Si) attracts interest as a substrate material for silicon device processing with the promise to yield single-crystalline silicon quality with multicrystalline silicon cost. A significant barrier to widespread implementation of QM-Si is ingot edge-contamination caused by the seed material and crucible walls during crystal growth. This work aims to recover the scrap material in QM-Si manufacturing with a process easily adaptable to semiconductor device manufacturing. A phosphorus diffusion process at 870 °C for 60 min significantly improves the electronic quality of a QM-Si wafer cut from a contaminated edge brick. The harmonic minority carrier recombination lifetime of the wafer, a key predictor of ultimate device performance, experiences a tenfold increase from 17 to 178 µs, which makes the scrap QM-Si material usable for device fabrication. Local areas with suboptimal (<50 µs) lifetimes remaining can be further improved by a high temperature anneal before the phosphorus diffusion process.

Designing a hetrostructure junctionless-field effect transistor (HJL-FET) for high-speed applications

Abstract: This paper explores the impacts of both the strained silicon layer thickness, D, and germanium mole fraction, X, on the electrical characteristics of a heterostructure junctionless (HJL)-FET by a numerical simulator. The gate controllability on the Si1−X Ge X layer has been increased by reducing D for a given X, hence, OFF-state current decreases. The permittivity factor increasing prevails to the band gap reducing in the Si0.3Ge0.7 layer, for D = 0.5 nm. As a result, in a 15 nm channel length, the OFF-state current of HJL-FET with D = 0.5 nm and X = 0.7 is improved by 95%, as compared to that of the regular JL-FET. Therefore, D and X parameters can be considered to reduce the OFF-state current of HJL-FET, even without pushing the gate to a large negative voltage. We propose a novel “Modified HJL-FET (MHJL-FET)” structure which improves the subthreshold slope (SS) in comparison with HJL-FET, by employing the doping engineering. The Si1−X Ge X layer of MHJL-FET has a lower doping density in comparison with the strained silicon layer. The doping engineering not only reduces SS by 10%, but also increases the ION/IOFF ratio two orders of magnitude, for 10 nm channel length. The benchmarking results indicate that the MHJL-FET device is promising for future logic transistor applications.

Capability of tip-enhanced Raman spectroscopy about nanoscale analysis of strained silicon for semiconductor devices production

Abstract: Localized strained silicon was observed with a suitable resolution in a real semiconductor device by tip-enhanced Raman spectroscopy (TERS). The device was made via a standard industrial process and its silicon trench isolation structures were used for the silicon strain analysis obtaining results according to finite element method-based simulation data. We have achieved a reliable and repeatable enhancement factor obtaining a trace of strained silicon along the structure with suitable nanometer spatial resolution compatible with IC industry requirements. We demonstrate that the complexity to analyze a real 3D structure, directly from the production lines and not ad hoc realized, entails the challenges to individuate the optimal tip shape, tip contact angle, tip composition, tip positioning system, laser power, and wavelength to achieve an appropriate plasmon resonance inducing a relevant signal to noise ratio. This work gives the base to address the development in TERS optimization for real industrial applications.

A Quasi-Static Model of Silicon Substrate Effects in Graphene Field Effect Transistors

Abstract: Investigations of the fundamental properties of graphene have leveraged the versatility of the CMOS fabrication platform early on by using oxidized semiconductor substrates with a highly doped back gate to behave as a metal gate down to cryogenic temperatures For future applications at room temperature and co-integration with standard silicon circuits, standard substrates should be considered and modeled Therefore, we investigate the impact of using standard lightly doped silicon as a back gate by building upon existing drift-diffusion models for the 3-terminal monolayer graphene field effect transistor Typical measurements of the back-gate transfer characteristics exhibit a kink/plateau around 0 V This effect is explained by the proposed model and corresponds to a loss of gate control occurring during the formation of the depletion layer in the substrate The impact is increased at low temperature, for thin oxides or under transient conditions

Transport Properties of Hydrogen-Terminated Silicon Surface Controlled by Ionic-Liquid Gating

Abstract: We fabricated electric double-layer transistors on the hydrogen-terminated (111)-oriented surface of non-doped silicon using ionic liquid as a gate dielectric. We introduced hole carriers into sili...

Method for making crystalline silicon-based solar cell, and method for making solar cell module

Abstract: A manufacturing method includes steps of forming a texture on a surface of a single-crystalline silicon substrate, cleaning the surface of the single-crystalline silicon substrate using ozone, depositing an intrinsic silicon-based layer on the texture on the single-crystalline silicon substrate, and depositing a conductive silicon-based layer on the intrinsic silicon-based layer, in this order. The single-crystalline silicon substrate before deposition of the intrinsic silicon-based layer has a texture size of less than 5 μm. A recess portion of the texture has a curvature radius of less than 5 nm. After deposition of at least a part of the intrinsic silicon-based layer and before deposition of the conductive silicon-based layer, the intrinsic silicon-based layer is subjected to a plasma treatment in an atmosphere of a gas mainly composed of hydrogen.