Showing papers on "Transistor published in 2011"
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
2,390 citations
TL;DR: In this article, the electron transport properties of group III-V compound semiconductors have been used for the development of the first nanometre-scale logic transistors, which is the first step towards the first IC transistors.
Abstract: For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.
1,446 citations
TL;DR: This simulation results show that while MoS(2) transistors may not be ideal for high-performance applications due to heavier electron effective mass and a lower mobility, they can be an attractive alternative for low power applications thanks to the large band gap and the excellent electrostatic integrity inherent in a two-dimensional system.
Abstract: Monolayer molybdenum disulfide (MoS2), unlike its bulk form, is a direct band gap semiconductor with a band gap of 1.8 eV. Recently, field-effect transistors have been demonstrated experimentally using a mechanically exfoliated MoS2 monolayer, showing promising potential for next generation electronics. Here we project the ultimate performance limit of MoS2 transistors by using nonequilibrium Green’s function based quantum transport simulations. Our simulation results show that the strength of MoS2 transistors lies in large ON–OFF current ratio (>1010), immunity to short channel effects (drain-induced barrier lowering ∼10 mV/V), and abrupt switching (subthreshold swing as low as 60 mV/decade). Our comparison of monolayer MoS2 transistors to the state-of-the-art III–V materials based transistors, reveals that while MoS2 transistors may not be ideal for high-performance applications due to heavier electron effective mass (m* = 0.45m0) and a lower mobility, they can be an attractive alternative for low power...
1,397 citations
TL;DR: This Perspective analyzes some of the most exciting strategies recently suggested in the design and structural organization of π-functional materials for transistor and solar cell applications and places emphasis on the interplay between molecular structure, self-assembling properties, nanoscale and mesoscale ordering, and device efficiency parameters.
Abstract: Organic electronics are broadly anticipated to impact the development of flexible thin-film device technologies. Among these, solution-processable π-conjugated polymers and small molecules are proving particularly promising in field-effect transistors and bulk heterojunction solar cells. This Perspective analyzes some of the most exciting strategies recently suggested in the design and structural organization of π-functional materials for transistor and solar cell applications. Emphasis is placed on the interplay between molecular structure, self-assembling properties, nanoscale and mesoscale ordering, and device efficiency parameters. A critical look at the various approaches used to optimize both materials and device performance is provided to assist in the identification of new directions and further advances.
1,301 citations
IBM1
TL;DR: A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer.
Abstract: A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.
896 citations
TL;DR: In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue.
Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.
842 citations
TL;DR: The fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process has a well-controlled density and a unique morphology.
Abstract: Carbon nanotube thin-film transistors are expected to enable the fabrication of high-performance, flexible and transparent devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases). Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated, but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 µm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm(2) V(-1) s(-1) and an on/off ratio of 6 × 10(6). We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master-slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques.
695 citations
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
453 citations
TL;DR: This study provides important insight into the working principles and characteristics of piezotronic devices, as well as providing guidance for device design.
Abstract: Due to polarization of ions in crystals with noncentral symmetry, such as ZnO, GaN, and InN, a piezoelectric potential (piezopotential) is created in the crystal when stress is applied. Electronics fabricated using the inner-crystal piezopotential as a gate voltage to tune or control the charge transport behavior across a metal/semiconductor interface or a p-n junction are called piezotronics. This is different from the basic design of complimentary metal oxide semiconductor (CMOS) field-effect transistors and has applications in force and pressure triggered or controlled electronic devices, sensors, microelectromechanical systems (MEMS), human-computer interfacing, nanorobotics, and touch-pad technologies. Here, the theory of charge transport in piezotronic devices is investigated. In addition to presenting the formal theoretical frame work, analytical solutions are presented for cases including metal-semiconductor contact and p-n junctions under simplified conditions. Numerical calculations are given for predicting the current-voltage characteristics of a general piezotronic transistor: metal-ZnO nanowire-metal device. This study provides important insight into the working principles and characteristics of piezotronic devices, as well as providing guidance for device design.
446 citations
TL;DR: This work demonstrates an organic channel light-emitting transistor operating at low voltage, with low power dissipation, and high aperture ratio, in the three primary colors, comparable to that of polycrystalline-silicon backplane transistor-driven display pixels.
Abstract: Intrinsic nonuniformity in the polycrystalline-silicon backplane transistors of active matrix organic light-emitting diode displays severely limits display size. Organic semiconductors might provide an alternative, but their mobility remains too low to be useful in the conventional thin-film transistor design. Here we demonstrate an organic channel light-emitting transistor operating at low voltage, with low power dissipation, and high aperture ratio, in the three primary colors. The high level of performance is enabled by a single-wall carbon nanotube network source electrode that permits integration of the drive transistor and the light emitter into an efficient single stacked device. The performance demonstrated is comparable to that of polycrystalline-silicon backplane transistor-driven display pixels.
436 citations
TL;DR: In this paper, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage.
Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.
Book•
15 Jan 2011
TL;DR: Power Semiconductor Devices - Key Components for Efficient Electrical Energy Conversion Systems - as mentioned in this paper, where pin-Diodes, Schottky Diodes and Bipolar Transistors are key components for efficient electrical energy conversion systems.
Abstract: Power Semiconductor Devices - Key Components for Efficient Electrical Energy Conversion Systems.- Semiconductor Properties.- pn - Junctions.- Short introduction to power device technology.- pin-Diodes.- Schottky Diodes.- Bipolar Transistors.- Thyristors.- MOS Transistors.- IGBTs.- Packaging and Reliability of Power Devices.- Destructive Mechanisms in Power Devices.- Power Device Induced Oscillations and Electromagnetic Disturbances.- Power Electronic Systems.- Appendix.- Index.
TL;DR: In this article, the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters was investigated.
Abstract: We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.
TL;DR: In this paper, the authors present an overview of solid-state integrated circuit amplifiers approaching terahertz frequencies based on the latest device technologies which have emerged in the past several years.
Abstract: We present an overview of solid-state integrated circuit amplifiers approaching terahertz frequencies based on the latest device technologies which have emerged in the past several years. Highlights include the best reported data from heterojunction bipolar transistor (HBT) circuits, high electron mobility transistor (HEMT) circuits, and metamorphic HEMT (mHEMT) amplifier circuits. We discuss packaging techniques for the various technologies in waveguide modules and describe the best reported noise figures measured in these technologies. A consequence of THz transistors, namely ultra-low-noise at cryogenic temperatures, will be explored and results presented. We also present a short review of power amplifier technologies for the THz regime. Finally, we discuss emerging materials for THz amplifiers into the next decade.
Patent•
18 Aug 2011
TL;DR: In this paper, an integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first inputport, and the second transistor is also adapted to provide a path for current flowing through the first outputport when the first transistor is in its non-conductive state.
Abstract: An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.
01 Jan 2011
TL;DR: In this paper, the authors present a roadmap for the semiconductor industry from the transistor level up to 14 levels of metallic interconnect layers, which must handle the signal transport between transistors and with the outside world.
Abstract: In a move singular for the world’s industry, the semiconductor industry established a quantitative strategy for its progress with the establishment of the ITRS. In its 17th year, it has been extended in 2009 to the year 2024. We present some important and critical milestones with a focus on 2020. Transistor gate lengths of 5.6 nm with a 3 sigma tolerance of 1 nm clearly show the aggressive nature of this strategy, and we reflect on this goal on the basis of our 10 nm reference nanotransistor discussed in Sect.3.3. The roadmap treats in detail the total process hierarchy from the transistor level up through 14 levels of metallic interconnect layers, which must handle the signal transport between transistors and with the outside world. This hierarchy starts with a first-level metal interconnect characterized by a half-pitch (roughly the line width) of 14 nm, which is required to be applicable through intermediate layers with wiring lengths orders of magnitude longer than at the first local level. At the uppermost global level, the metal pattern has to be compatible with high-density through-silicon vias (TSV), in order to handle the 3D stacking of chips at the wafer level to achieve the functionality of the final chip-size product. At the individual wafer level, the full manufacturing process is characterized by up to 40 masks, thousands of processing steps and a cumulative defect density of hopefully <1/cm².
TL;DR: This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor-one memristor structure (1T-1M) by integration of a high-performance single crystal silicon transistor with a titanium oxide based Memristor without any electrical interference from adjacent cells.
Abstract: The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has recently increased due to their advantages over present rigid electronic systems. Flexible memory is an essential part of electronic systems for data processing, storage, and communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor–one memristor structure (1T-1M). By integration of a high-performance single crystal silicon transistor with a titanium oxide based memristor, random access to memory cells on flexible substrates was achieved without any electrical interference from adjacent cells. The work presented here can provide a new appr...
TL;DR: A new methodology for designing and implementing high-efficiency broadband Class-E power amplifiers (PAs) using high-order low-pass filter-prototype is proposed, which provides optimized fundamental and harmonic impedances within an octave bandwidth (L-band).
Abstract: A new methodology for designing and implementing high-efficiency broadband Class-E power amplifiers (PAs) using high-order low-pass filter-prototype is proposed in this paper. A GaN transistor is used in this work, which is carefully modeled and characterized to prescribe the optimal output impedance for the broadband Class-E operation. A sixth-order low-pass filter-matching network is designed and implemented for the output matching, which provides optimized fundamental and harmonic impedances within an octave bandwidth (L-band). Simulation and experimental results show that an optimal Class-E PA is realized from 1.2 to 2 GHz (50%) with a measured efficiency of 80%-89%, which is the highest reported today for such a bandwidth. An overall PA bandwidth of 0.9-2.2 GHz (84%) is measured with 10-20-W output power, 10-13-dB gain, and 63%-89% efficiency throughout the band. Furthermore, the Class-E PA is characterized through measurements using constant-envelop global system for mobile communications signals, indicating a favorable adjacent channel power ratio from -40 to -50 dBc within the entire bandwidth.
TL;DR: In this article, the authors derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field effect transistor (DG MOSFET) device.
Abstract: We derived an analytical model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge-potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm-3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.
TL;DR: In this article, the authors simulate and experimentally investigate the source-pocket tunnel field effect transistor (TFET), which is based on the principle of band-to-band tunneling.
Abstract: Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.
TL;DR: In this paper, the electrical properties of the junctionless field effect transistor (FET) have been modeled and a constraint on the allowable value of the doping density per unit length and its impact on the overall device performance is discussed.
Abstract: In this paper, we model the electrical properties of the junctionless (JL) nanowire field-effect transistor (FET), which has been recently proposed as a possible alternative to the junction-based FET. The analytical model worked out here assumes a cylindrical geometry and is meant to provide a physical understanding of the device behavior. Most notably, it aims to clarify the motivation for its nearly ideal subthreshold slope and its excellent on-state current while being a depletion device with lower electron mobility due to impurity scattering. At the same time, the model clarifies a constraint binding the allowable value of the doping density per unit length and its impact on the overall device performance. The device variability and the parasitic source/drain resistances are identified as the most important limitations of the JL nanowire field-effect transistor.
TL;DR: This paper proposes a novel design style Pseudo-CMOS for flexible electronics that uses only monotype single-VT TFTs but has comparable performance with the complementary-type or dual-VT designs.
Abstract: Thin-film transistors (TFTs) are a key element of flexible electronics implemented on low-cost substrates. Most TFT technologies, however, have only monotype-either n- or p-type-devices. In this paper, we propose a novel design style Pseudo-CMOS for flexible electronics that uses only monotype single-VT TFTs but has comparable performance with the complementary-type or dual-VT designs. The manufacturing cost and complexity can therefore be significantly reduced, whereas the circuit yield and reliability are enhanced with built-in postfabrication tunability. Digital cells are fabricated in two different TFT technologies, i.e., p-type self-assembled-monolayer-organic TFTs and n-type metal-oxide InGaZnO TFTs, to validate the proposed Pseudo-CMOS design style. To the best of our knowledge, this is the first design solution that has been experimentally proven to achieve superior performance for both types of TFT technologies.
TL;DR: These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes, which makes them very suitable for the multiple- V t design method.
Abstract: Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple- V t design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40 less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.
TL;DR: In the inaugural issue of this Journal, Indiveri et al. (2011) review the current state of the art in CMOS-based neuromorphic neuron circuit designs that have evolved over the past two decades and delineates and compares the latest SiN design techniques as applied to varying types of spiking neuron models ranging from realistic conductancebased Hodgkin–Huxley models to simple yet versatile integrate-and-fire models.
Abstract: Neuromorphic silicoN NeuroNs: state of the art Complementary metal-oxide-semiconductor (CMOS) transistors are commonly used in very-large-scale-integration (VLSI) digital circuits as a basic binary switch that turns on or off as the transistor gate voltage crosses some threshold. Carver Mead first noted that CMOS transistor circuits operating below this threshold in current mode have strikingly similar sigmoidal current– voltage relationships as do neuronal ion channels and consume little power; hence they are ideal analogs of neuronal function (Mead, 1989). This unique device physics led to the advent of “neuromorphic” silicon neurons (SiNs) which allow neuronal spiking dynamics to be directly emulated on analog VLSI chips without the need for digital software simulation (Mahowald and Douglas, 1991). In the inaugural issue of this Journal, Indiveri et al. (2011) review the current state of the art in CMOS-based neuromorphic neuron circuit designs that have evolved over the past two decades. The comprehensive appraisal delineates and compares the latest SiN design techniques as applied to varying types of spiking neuron models ranging from realistic conductancebased Hodgkin–Huxley models to simple yet versatile integrate-and-fire models. The timely and much needed compendium is a tour de force that will certainly provide a valuable guidepost for future SiN designs and applications.
TL;DR: The bulk planar junctionless transistor (BPJLT) as mentioned in this paper is a novel source-drain-junction-free field effect transistor (SJFFL) based on the idea of an isolated ultrathin highly doped device layer of which volume is fully depleted in the off-state and is around flatband in the on-state.
Abstract: We propose a novel highly scalable source-drain-junction-free field-effect transistor that we call the bulk planar junctionless transistor (BPJLT). This builds upon the idea of an isolated ultrathin highly doped device layer of which volume is fully depleted in the off-state and is around flatband in the on-state. Here, the leakage current depends on the effective device layer thickness, and we show that with well doping and/or well bias, this can be controllably made less than the physical device layer thickness in a bulk planar junction-isolated structure. We demonstrate by extensive device simulations that these additional knobs for controlling short-channel effects reduce the off-state leakage current by orders of magnitude for similar on-state currents, making the BPJLT highly scalable.
TL;DR: Organic transistors and circuits are fabricated directly on the surface of banknotes with a yield of 92% and have a field-effect mobility of about 0.2 cm2 V−1s−1.
Abstract: Organic transistors and circuits are fabricated directly on the surface of banknotes. The transistors operate with voltages of 3 V and have a field-effect mobility of about 0.2 cm2 V−1s−1. For an array of 100 transistors a yield of 92% is obtained.
TL;DR: In this article, the authors present a background describing THz monolithic integrated circuits using InP HEMT, which has been used to realize amplifiers, mixers, and multipliers operating at 670 GHz.
Abstract: In this paper, background describing THz monolithic integrated circuits using InP HEMT is presented. This three-terminal transistor technology has been used to realize amplifiers, mixers, and multipliers operating at 670 GHz. Transistor and processing technology, packaging technology, and circuit results at 670 GHz are described. The paper concludes with initial results from a 670-GHz InP HEMT receiver and trends for InP HEMT components.
TL;DR: In this article, the fundamental edge configurations together with the role of various types of edge defects and their effects on graphene properties are discussed, and major demanding challenges to find the most suitable technique to characterize graphene edges for numerous device applications such as transistors, sensors, actuators, solar cells, light-emitting displays, and batteries in graphene technology.
Abstract: Graphene edges determine the optical, magnetic, electrical, and electronic properties of graphene. In particular, termination, chemical functionalization and reconstruction of graphene edges leads to crucial changes in the properties of graphene, so control of the edges is critical to the development of applications in electronics, spintronics and optoelectronics. Up to date, significant advances in studying graphene edges have directed various smart ways of controlling the edge morphology. Though, it still remains as a major challenge since even minor deviations from the ideal shape of the edges significantly deteriorate the material properties. In this review, we discuss the fundamental edge configurations together with the role of various types of edge defects and their effects on graphene properties. Indeed, we highlight major demanding challenges to find the most suitable technique to characterize graphene edges for numerous device applications such as transistors, sensors, actuators, solar cells, light-emitting displays, and batteries in graphene technology.
TL;DR: The advantages of printed electronics and semiconducting single-walled carbon nanotubes (SWCNTs) are combined for the first time for display electronics and the successful control over external OLED is demonstrated.
Abstract: The advantages of printed electronics and semi- conducting single-walled carbon nanotubes (SWCNTs) are combined for the first time for display electronics. Conductive silver ink and 98% semiconductive SWCNT solutions are used to print back-gated thin film transistors with high mobility, high on/off ratio, and high current carrying capacity. In addition, with printed polyethylenimine with LiClO4 as the gating material, fully printed top-gated devices have been made to work as excellent current switches for organic light emitting diodes (OLEDs). An OLED driving circuit composed of two top-gated fully printed transistors has been fabricated, and the successful control over external OLED is demonstrated. Our work demonstrates the significant potential of using printed carbon nanotube electronics for display backplane applications.
IBM1
TL;DR: This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures.
Abstract: While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.