Showing papers on "Wafer published in 2020"

Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)

Abstract: Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore’s law of the number of transistors in an integrated circuit1. One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering2,3. Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces4 or bulk copper foils5. However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films6,7. Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)5,8 is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics. The epitaxial growth of single-crystal hexagonal boron nitride monolayers on a copper (111) thin film across a sapphire wafer suggests a route to the broad adoption of two-dimensional layered semiconductor materials in industry.

Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics.

Abstract: Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production of dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion and sorting process that resulted in extremely high semiconducting purity and a dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT arrays (within alignment of 9 degrees) with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer. Top-gate field-effect transistors (FETs) fabricated on the CNT array show better performance than that of commercial silicon metal oxide-semiconductor FETs with similar gate length, in particular an on-state current of 1.3 milliamperes per micrometer and a recorded transconductance of 0.9 millisiemens per micrometer for a power supply of 1 volt, while maintaining a low room-temperature subthreshold swing of 8 gigahertz.

Wafer-Scale Highly Oriented Monolayer MoS2 with Large Domain Sizes.

Abstract: Two-dimensional molybdenum disulfide (MoS2) is an emergent semiconductor with great potential in next-generation scaled-up electronics, but the production of high-quality monolayer MoS2 wafers still remains a challenge. Here, we report an epitaxy route toward 4 in. monolayer MoS2 wafers with highly oriented and large domains on sapphire. Benefiting from a multisource design for our chemical vapor deposition setup and the optimization of the growth process, we successfully realized material uniformity across the entire 4 in. wafer and greater than 100 μm domain size on average. These monolayers exhibit the best electronic quality ever reported, as evidenced from our spectroscopic and transport characterizations. Our work moves a step closer to practical applications of monolayer MoS2.

A Deep Convolutional Neural Network for Wafer Defect Identification on an Imbalanced Dataset in Semiconductor Manufacturing Processes

Abstract: Wafer maps contain information about various defect patterns on the wafer surface and automatic classification of these defects plays a vital role to find their root causes. Semiconductor engineers apply various methods for wafer defect classification such as manual visual inspection or machine learning-based algorithms by manually extracting useful features. However, these methods are unreliable, and their classification performance is also poor. Therefore, this paper proposes a deep learning-based convolutional neural network for automatic wafer defect identification (CNN-WDI). We applied a data augmentation technique to overcome the class-imbalance issue. The proposed model uses convolution layers to extract valuable features instead of manual feature extraction. Moreover, state-of-the-art regularization methods such as batch normalization and spatial dropout are used to improve the classification performance of the CNN-WDI model. The experimental results comparison using a real wafer dataset shows that our model outperformed all previously proposed machine learning-based wafer defect classification models. The average classification accuracy of the CNN-WDI model with nine different wafer map defects is 96.2%, which is an increment of 6.4% from the last highest average accuracy using the same dataset.

Wafer-scale low-loss lithium niobate photonic integrated circuits

Abstract: Thin-film lithium niobate (LN) photonic integrated circuits (PICs) could enable ultrahigh performance in electro-optic and nonlinear optical devices. To date, realizations have been limited to chip-scale proof-of-concepts. Here we demonstrate monolithic LN PICs fabricated on 4- and 6-inch wafers with deep ultraviolet lithography and show smooth and uniform etching, achieving 0.27 dB/cm optical propagation loss on wafer-scale. Our results show that LN PICs are fundamentally scalable and can be highly cost-effective.

Layer-controlled single-crystalline graphene film with stacking order via Cu–Si alloy formation

Abstract: Multilayer graphene and its stacking order provide both fundamentally intriguing properties and technological engineering applications. Several approaches to control the stacking order have been demonstrated, but a method of precisely controlling the number of layers with desired stacking sequences is still lacking. Here, we propose an approach for controlling the layer thickness and crystallographic stacking sequence of multilayer graphene films at the wafer scale via Cu-Si alloy formation using direct chemical vapour deposition. C atoms are introduced by tuning the ultra-low-limit CH4 concentration to form a SiC layer, reaching one to four graphene layers at the wafer scale after Si sublimation. The crystallographic structure of single-crystalline or uniformly oriented bilayer (AB), trilayer (ABA) and tetralayer (ABCA) graphene are determined via nano-angle-resolved photoemission spectroscopy, which agrees with theoretical calculations, Raman spectroscopy and transport measurements. The present study takes a step towards the layer-controlled growth of graphite and other two-dimensional materials.

Large and Dense Organic-Inorganic Hybrid Perovskite CH3NH3PbI3 Wafer Fabricated by One-Step Reactive Direct Wafer Production with High X-ray Sensitivity.

Abstract: Lead halide perovskites with good optoelectronic properties and high attenuation of high-energy radiation are great candidates for X-ray radiation detectors. Large area, dense, and thick films or w...

Remote heteroepitaxy of GaN microrod heterostructures for deformable light-emitting diodes and wafer recycle

Abstract: There have been rapidly increasing demands for flexible lighting apparatus, and micrometer-scale light-emitting diodes (LEDs) are regarded as one of the promising lighting sources for deformable device applications. Herein, we demonstrate a method of creating a deformable LED, based on remote heteroepitaxy of GaN microrod (MR) p-n junction arrays on c-Al2O3 wafer across graphene. The use of graphene allows the transfer of MR LED arrays onto a copper plate, and spatially separate MR arrays offer ideal device geometry suitable for deformable LED in various shapes without serious device performance degradation. Moreover, remote heteroepitaxy also allows the wafer to be reused, allowing reproducible production of MR LEDs using a single substrate without noticeable device degradation. The remote heteroepitaxial relation is determined by high-resolution scanning transmission electron microscopy, and the density functional theory simulations clarify how the remote heteroepitaxy is made possible through graphene.

MoS2 radio: detecting radio waves with a two-dimensional transition metal dichalcogenide semiconductor.

Abstract: In this letter, we have designed, fabricated and tested a microwave circuit based on a MoS2 self-switching diode. The MoS2 thin film (10-monolayers nominal thickness) was grown on a 4-inch Al2O3/high-resistivity silicon wafer by Chemical Vapor Deposition process. The Raman measurements confirm the high quality of the MoS2 over the whole area of the 4-inch wafer. We show experimentally that a microwave circuit based on a few-layers MoS2 self-switching diode fabricated at the wafer level is able to detect the audio spectrum from amplitude-modulated microwave signals in the band 0.9-10 GHz, i.e. in the frequency range mostly used by current wireless communications. In particular, the 900 MHz band is widely exploited for GSM applications, whereas the 3.6 GHz band has been identified as the primary pioneer band for 5G in the European Union

Deformable Convolutional Networks for Efficient Mixed-Type Wafer Defect Pattern Recognition

Abstract: Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries. During wafer fabrication, several types of defects can be coupled together in a piece of wafer, it is called mixed-type defects DPR. To detect mixed-type defects is much more complicated because the combination of defects may vary a lot, from the type of defects, position, angle, number of defects, etc. Deep learning methods have been a good choice for complex pattern recognition problems. In this article, we propose a deformable convolutional network (DC-Net) for mixed-type DPR (MDPR) in which several types of defects are coupled together in a piece of wafer. A deformable convolutional unit is designed to selectively sample from mixed defects, then extract high-quality features from wafer maps. A multi-label output layer is improved with a one-hot encoding mechanism, which decomposes extract mixed features into each basic single defect. The experiment results indicate that the proposed DC-Net model outperforms conventional models and other deep learning models. Further results of the interpretable analysis reveal that the proposed DC-Net can accurately pinpoint the defects areas of wafer maps with noise points, which is beneficial for mixed-type DPR problems.

A Light-Weighted CNN Model for Wafer Structural Defect Detection

Abstract: Silicon wafer is the raw material of semiconductor chip. It is important and challenging to research a fast and accurate method of identifying and classifying wafer structural defects. To this end, we present a novel detection method in terms of the convolution neural networks (CNN), which achieve more than 99% detection accuracy. Due to the wafer images are not available by open datasets, a set of imaging acquisition system is designed to capture wafer images. Digital image preprocessing technology is utilized to split a wafer image into thousands of silicon grain images. The proposed model, called WDD-Net, uses depthwise separable convolutions and global average pooling to reduce parameters and calculations, adopts multiple 1*1 standard convolutions to increase the network depth. Specifically, two types of CNN models, VGG-16 and MobileNet-v2, are adopted for comparative analysis. Using the aforementioned three models, the comparative experiments are implemented on data sets that consisting of more than ten thousand grain images. The experimental results show that compared with VGG-16 and MobileNet-v2, the detection speed of the WDD-Net is 105.6FPS, which is 5 times faster. The model size of the WDD-Net is 307KB, which is much smaller than the other two. Furthermore, the WDD-Net directly completes the data collection and defect detection process through the local computing equipment, which is suitable for edge computing.

A review on chemical and mechanical phenomena at the wafer interface during chemical mechanical planarization

Abstract: As the minimum feature size of integrated circuit elements has shrunk below 7 nm, chemical mechanical planarization (CMP) technology has grown by leaps and bounds over the past several decades. There has been a growing interest in understanding the fundamental science and technology of CMP, which has continued to lag behind advances in technology. This review paper provides a comprehensive overview of various chemical and mechanical phenomena such as contact mechanics, lubrication models, chemical reaction that occur between slurry components and films being polished, electrochemical reactions, adsorption behavior and mechanism, temperature effects, and the complex interactions occurring at the wafer interface during polishing. It also provides important insights into new strategies and novel concepts for next‐generation CMP slurries. Finally, the challenges and future research directions related to the chemical and mechanical process and slurry chemistry are highlighted.

Wafer-Scale and Low-Temperature Growth of 1T-WS2 Film for Efficient and Stable Hydrogen Evolution Reaction

Abstract: The metallic 1T phase of WS2 (1T-WS2 ), which boosts the charge transfer between the electron source and active edge sites, can be used as an efficient electrocatalyst for the hydrogen evolution reaction (HER). As the semiconductor 2H phase of WS2 (2H-WS2 ) is inherently stable, methods for synthesizing 1T-WS2 are limited and complicated. Herein, a uniform wafer-scale 1T-WS2 film is prepared using a plasma-enhanced chemical vapor deposition (PE-CVD) system. The growth temperature is maintained at 150 °C enabling the direct synthesis of 1T-WS2 films on both rigid dielectric and flexible polymer substrates. Both the crystallinity and number of layers of the as-grown 1T-WS2 are verified by various spectroscopic and microscopic analyses. A distorted 1T structure with a 2a0 × a0 superlattice is observed using scanning transmission electron microscopy. An electrochemical analysis of the 1T-WS2 film demonstrates its similar catalytic activity and high durability as compared to those of previously reported untreated and planar 1T-WS2 films synthesized with CVD and hydrothermal methods. The 1T-WS2 does not transform to stable 2H-WS2 , even after a 700 h exposure to harsh catalytic conditions and 1000 cycles of HERs. This synthetic strategy can provide a facile method to synthesize uniform 1T-phase 2D materials for electrocatalysis applications.

100 GHz zinc oxide Schottky diodes processed from solution on a wafer scale

Abstract: Inexpensive radio-frequency devices that can meet the ultrahigh-frequency needs of fifth- and sixth-generation wireless telecommunication networks are required. However, combining high performance with cost-effective scalable manufacturing has proved challenging. Here, we report the fabrication of solution-processed zinc oxide Schottky diodes that can operate in microwave and millimetre-wave frequency bands. The fully coplanar diodes are prepared using wafer-scale adhesion lithography to pattern two asymmetric metal electrodes separated by a gap of around 15 nm, and are completed with the deposition of a zinc oxide or aluminium-doped ZnO layer from solution. The Schottky diodes exhibit a maximum intrinsic cutoff frequency in excess of 100 GHz, and when integrated with other passive components yield radio-frequency energy-harvesting circuits that are capable of delivering output voltages of 600 mV and 260 mV at 2.45 GHz and 10 GHz, respectively. Nanoscale electrodes fabricated using adhesion lithography can be combined with solution-processed metal oxide semiconductors to create Schottky diodes with performance suitable for 5G communications and beyond.

Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits

Abstract: Author(s): Kreikebaum, JM; O'Brien, KP; Morvan, A; Siddiqi, I | Abstract: Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of 30%. Inferring a critical current ≡σIc≪Ic≫ variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in l 3.5% relative standard deviation (RSD) in critical current () for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having l 1.0% (equivalent to l 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.

Low frequency noise characteristics of resistor- and Si MOSFET-type gas sensors fabricated on the same Si wafer with In2O3 sensing layer

Abstract: By analyzing the Low Frequency Noise (LFN) characteristics of the resistor-type and the Si metal oxide semiconductor Field Effect Transistor (FET)-type gas sensors fabricated on the same wafer, the intrinsic device noise and the additional noise generated from the gas reaction are systemically examined. Sensing material, n-type Indium-Oxide (In2O3) film, is deposited using the radio frequency magnetron sputtering method. Unlike the FET-type gas sensor, the LFN characteristics of the resistor-type gas sensor are affected by the deposition condition of the sensing material. It is shown that the FET-type sensor has at least 10 times less LFN power than the resistor-type gas sensor despite its smaller size. Gas to Air Noise Ratio (GANR) is introduced as a new figure of merit to evaluate and compare the LFN characteristics during the gas reaction in both resistor- and FET-type gas sensors with the sensing layer prepared by different process conditions. The GANRs of the resistor-type sensors range from ∼2 to 4, which demonstrates that the reaction between the gas molecules and the sensing material generates a fluctuation that exceeds the intrinsic noise of devices. However, the FET-type gas sensors have a constant value of GANR (∼1) regardless of the operation region, showing that the FET-type gas sensors have better performance in terms of noise.

CMOS-compatible a-Si metalenses on a 12-inch glass wafer for fingerprint imaging

Abstract: Abstract Metalenses made of artificial sub-wavelength nanostructures have shown the capability of light focusing and imaging with a miniaturized size. Here, we report the demonstration of mass-producible amorphous silicon metalenses on a 12-inch glass wafer via the complementary metal-oxide-semiconductor compatible process. The measured numerical aperture of the fabricated metalens is 0.496 with a focusing spot size of 1.26 μm at the wavelength of 940 nm. The metalens is applied in an imaging system to test the imaging resolution. The minimum bar of the resolution chart with a width of 2.19 μm is clearly observed. Furthermore, the same system demonstrates the imaging of a fingerprint, and proofs the concept of using metalens array to reduce the system size for future compact consumer electronics.

Large-Area Exfoliated Lead-Free Perovskite-Derivative Single-Crystalline Membrane for Flexible Low-Defect Photodetectors.

Abstract: Wide applications of personal consumer electronics have tended to cause a huge demand for smart and portable electronics, featuring mechanical flexibility, lightweight, and environmental friendliness. However, most of the recently reported flexible photodetectors based on microcrystalline and amorphous components commonly suffer from severe drawbacks, including plenty of grains, boundaries, and surface defects. Here, we present a new lead-free chiral perovskite-derivative light absorber of (aminoguanidinium)3Bi2I9 (AG3Bi2I9), which displays a narrow direct band gap of about 1.89 eV. High-quality bulk single crystals were successfully grown with dimensions up to 24 × 12 × 5 mm3. Emphatically, as-grown bulk single crystals are easy to be exfoliated for large-area ultrathin wafers with an exfoliated area up to 0.6 cm2, showing promise for low-defect flexible optoelectronic applications. The remarkable surface smoothness and crystalline quality of single-crystalline thin layers were further confirmed by TEM, HRTEM, AFM, single-crystalline X-ray diffraction, and space-charge limited current (SCLC) measurements. As expected, the planar photodetectors based on flexible exfoliated wafers are first fabricated and exhibit notable photoelectric performance. This work represents an important step forward as it offers an effective strategy for the fabrication of high-quality large-area flexible exfoliated wafer devices.

Multiwavelength membrane laser array using selective area growth on directly bonded InP on SiO2/Si

Abstract: The cost and power consumption of optical transmitters are now hampering further increases in total transmission capacity within and between data centers Photonic integrated circuits (PICs) based on silicon (Si) photonics with wavelength-division multiplexing (WDM) technologies are promising solutions However, due to the inefficient light emission characteristics of Si, incorporating III-V compound semiconductor lasers into PICs via a heterogeneous integration scheme is desirable In addition, optimizing the bandgap of the III-V material used for each laser in a WDM transmitter becomes important because of recent strict requirements for optical transmitters in terms of data speed and operating temperature Given these circumstances, applying a direct-bonding scheme is very difficult because it requires multiple bonding steps to bond different-bandgap III-V materials that are individually grown on different wafers Here, to achieve wideband WDM operation with a single wafer, we employ a selective area growth technique that allows us to control the bandgap of multi-quantum wells (MQWs) on a thin InP layer directly bonded to silicon (InP-on-insulator) The InP-on-insulator platform allows for epitaxial growth without the fundamental difficulties associated with lattice mismatch or antiphase boundaries High crystal quality is achieved by keeping the total III-V layer thickness less than the critical thickness (430 nm) and compensating for the thermally induced strain in the MQWs By carrying out one selective MQW growth, we successfully fabricated an eight-channel directly modulated membrane laser array with lasing wavelengths ranging from 12723 to 13105 nm The fabricated lasers were directly modulated at 56-Gbit/s with pulse amplitude modulation with four-amplitude-level signal This heterogeneous integration approach paves the way to establishing III-V/Si WDM-PICs for future data-center networks

On-wafer fabrication of etched-mirror UV-C laser diodes with the ALD-deposited DBR

Abstract: We have demonstrated an on-wafer fabrication process for AlGaN-based UV-C laser diodes (LDs) with etched mirrors and have achieved lasing for 100 ns pulsed current injection at room temperature. A combined process of dry and wet etching was employed to achieve smooth and vertical AlGaN (1 1 ¯00) facets. These etched facets were then uniformly coated with a distributed Bragg reflector by atomic layer deposition. A remarkable reduction of the lasing threshold current density to 19.6 kA / cm 2 was obtained owing to the high reflectivity of the etched and coated mirror facets. The entire laser diode fabrication process was carried out on a whole 2-in. wafer. We propose this mirror fabrication process as a viable low-cost AlGaN-based UV-C LD production method that is also compatible with highly integrated optoelectronics based on AlN substrates.