Showing papers on "p–n junction published in 1995"

Metal oxide semiconductor device forming a pn junction with a thin film transistor of metal oxide semiconductor of copper suboxide and manufacture thereof

Abstract: PURPOSE: To obtain an excellent PN junction by doping controlled metal oxide semiconductor with impurities, by controlling defects by introducing hydrogen or the like in the defects due to the excessive oxygen in a part of metal oxide semiconductor of copper suboxide or the like, and controlling the carrier density and the conductivity type. CONSTITUTION: A metal oxide semiconductor 25 is metal semiconductor obtained by oxidizing metal films 24, 24'. An insulating protective film is formed on the surfaces of an insulating film 26 and the metal oxide semiconductor 25. By leading out electrodes connected with source drain electrodes 24, 24', a transistor having a gate electrode 22 is formed. The carrier density and the conductivity type are controlled by eliminating oxygen defects. The P-type conductivity or the N-type conductivity, and the resistivity can be controlled by impurity doping. In these cases, ion implantation method or the like can be applied. Thereby a thin film transistor of high mobility can be formed in a large area by low temperature treatment.

Silicon pn junction imaging and characterizations using sensitivity enhanced Kelvin probe force microscopy

Abstract: We observed the surface potential of silicon pn junctions using a Kelvin probe force microscope whose sensitivity was about five times better than that of a conventional one. It was achieved by three major improvements: electrostatic force detection using the second cantilever resonance, cantilever Q‐value enhancement by operating in a vacuum, and direct cantilever resonance frequency detection using the frequency modulation technique. It was demonstrated that the surface potential of the pn junctions made by thermal diffusion varies gradually compared to those made by ion implantation, possibly reflecting their gradual dopant concentration profile.

Gallium nitride group compound semiconductor laser diode

Abstract: A gallium nitride group compound semiconductor laser diode includes at least one pn junction layer disposed between an n-type layer and a p-type layer. The n-type layer is formed from a gallium nitride group compound semiconductor material defined by the composition equation (Alx Ga1-x)y In1-y N (where 0≦x≦1 and 0≦y≦1). The p-type layer, doped with an acceptor impurity, is obtained by electron beam irradiating a gallium nitride group compound semiconductor material defined by the composition equation (Alx' Ga1-x')y' In1-y' N (where 0≦x'≦1, 0≦y'≦1, x=x' or x≠x', and, y=y' or y≠y'). The improved gallium nitride group semiconductor laser diode of the present invention is found to emit light in the visible short wavelength spectrum of light which includes the blue, violet and ultraviolet regions.

Field effect transistor

Abstract: A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.

PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof

Abstract: Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl 3 doping are required to fabricate this device. The threshold voltage of this device is well controlled by the ratio of C fp , capacitance of the P type capacitor and C fn capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

Improvement in HgCdTe diode characteristics by low temperature post-implantation annealing

Abstract: Hg1−xCdxTe diodes (x∼0.22) with different carrier concentrations in p type materials have been fabricated by employing an ion-implantation technique. The performances of the diodes, prior to and after low temperature postimplantation annealing, have been investigated in detail by model fitting, taking into account dark current mechanisms. Prior to the annealing process, dark currents for diodes with relatively low carrier concentrations are found to be limited by generation-recombination current and trap-assisted tunneling current, while dark currents for diodes with higher carrier concentrations are limited by band-to-band tunneling current. These dark currents in both diodes have been dramatically decreased by the low temperature annealing at 120∼150°C. From the model fitting analyses, it turned out that trap density and the density of the surface recombination center in the vicinity of the pn junction were reduced by one order of magnitude for a diode with lower carrier concentration and that the carrier concentration profile in a pn junction changed for a diode with higher carrier concentration. The improvements are explained by changes in both carrier concentration profile and pn junction position determined by interaction of interstitial Hg with Hg vacancy in the vicinity of the junction during the annealing process.

PN junction formation in 6HSiC by acceptor implantation into n-type substrate

Abstract: A1 and B implantations were performed into n-type 6H-bulk SiC and epitaxial layers at both room temperature and 850°C. Annealings were performed in the temperature range of 1100–1650°C in a SiC crucible. For single-energy implants, the implant gettered to the 0.7Rp location for annealing temperatures ≥1400°C. For the 850°C implanted samples the RBS yield in the annealed material is comparable to the yield in the as-grown material, indicating a good lattice recovery. A maximum activation of 18% for Al-implanted samples was observed. PN junction diodes were made using Al-implanted material.

Analysis of nonideal Schottky and p‐n junction diodes—Extraction of parameters from I–V plots

Abstract: We propose two novel methods of determining nonideal Schottky and p‐n junction diodes parameters from I–V plots. The series resistance Rs, saturation current Is, as well as the bias‐dependent ideality factor n(V), can be obtained from two successive I–V measurements—one solely of the diode and the other with an external resistance added in series with the measured diode. Our analysis confirms that the methods produce accurate and reliable results even when the conventional techniques fail, such as when we have strongly varying function n(V) in the presence of series resistance and an experimental noise.

The frequency response of porous silicon electroluminescent devices

Abstract: Under a constant forward bias, porous silicon light‐emitting devices (LEDs) produce stable electroluminescence (EL) that is detectable at applied voltages as low as 5 V and visible in daylight at higher voltages. The recombination dynamics of the EL are studied and correlated to the photoluminescence properties of light‐emitting porous silicon (LEPSi). The EL efficiency is related to the LEPSi properties and the device configuration. LEPSi LEDs with an EL efficiency of 0.01% have been achieved. The frequency response of the EL to a modulating ac bias is measured. For metal/LEPSi LEDs, the −3 dB frequency is determined by the carrier transit time which must be larger than the carrier lifetime to achieve efficient EL. For LEPSi pn junction LEDs, the −3 dB frequency is determined only by the carrier lifetime and can be in excess of 200 kHz.

Semiconductor tunnel junction with enhancement layer

Abstract: The incorporation of a pseudomorphic GaAsSb layer in a runnel diode structure affords a new degree of freedom in designing runnel junctions for p-n junction device interconnects. Previously only doping levels could be varied to control the tunneling properties. This invention uses the valence band alignment band of the GaAsSb with respect to the surrounding materials to greatly relax the doping requirements for tunneling.

Plasma‐induced damage of GaAs pn‐junction diodes using electron cyclotron resonance generated Cl2/Ar, BCl3/Ar, Cl2/BCl3/Ar, and SiCl4/Ar plasmas

Abstract: Plasma‐induced etch damage often degrades the electrical and optical performance of III–V high‐density integrated circuits and photonic devices. We have investigated the etch‐induced damage of electron cyclotron resonance (ECR) generated plasmas on the electrical performance of mesa‐isolated GaAs pn‐junction diodes. Cl2/Ar, BCl3/Ar, Cl2/BCl3/Ar, and SiCl4/Ar ECR plasmas at ion energies ranging from 10 to 200 eV were studied. Diodes fabricated under low dc‐bias (≤100 V) etch conditions yielded low reverse‐bias currents which were comparable to wet‐chemical‐etched devices. As the dc bias was increased, the diodes showed significantly higher reverse‐bias currents indicating plasma‐induced sidewall damage of the pn‐junction. Variations in diode reverse‐bias leakage currents are reported as a function of plasma parameters and chemistries.

A mechanism and a reduction technique for large reverse leakage current in p-n junctions

Abstract: The origin of anomalously large p-n junction leakage current in Si is investigated. The leakage has strong electric field dependence and weak temperature dependence, and therefore cannot be explained by either generation-recombination current or diffusion current. It may be explained by the local Zener effect at local enhancement of the electric field around small precipitates in the depletion layer. Supposing a spherical precipitate, the electric field will be enhanced as much as 1.3 times for a SiO/sub 2/ precipitate and 3 times for a metal precipitate. The leakage features are explained by the electric field dependence and the temperature dependence of the local Zener probability. A new approach to reduce the local Zener probability by controlling the profile of the electric field is proposed, and the validity of the approach is confirmed by direct experiment and by improvement in the refresh operation of DRAM cells. >

Nonvolatile memory cell with P-N junction formed in polysilicon floating gate

Abstract: An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages VT, and improves device life because fewer electrons travel through the gate oxide (30).

Planar, ion implanted, high voltage 6H-SiC P-N junction diodes

Abstract: Planar, high voltage (800 V) P-N junction diodes have been fabricated for the first time on N-type 6H-SiC by room temperature boron implantation through a pad oxide deposited within windows etched in an LPCVD field oxide. All the diodes showed excellent rectification with leakage currents of less than 10 nA (/spl sim/5/spl times/10/sup -5/ A/cm/sup 2/) until avalanche breakdown. It was found that the breakdown voltage increases with junction depth. The reverse recovery time (t/sub rr/) was measured to be 50 ns for the 800 V diode from which an effective minority carrier life time of 12.5 ns was extracted. >

High-temperature diamond p-n junction: b-doped homoepitaxial layer on n-doped substrate

Abstract: Boron‐doped homoepitaxial layers have been selectively grown on synthetic type Ib substrates of (100) cut. Ohmic contacts were formed by evaporating a Mo/Pt/Au sandwich and subsequent annealing at 950°C for h. Current–voltage characteristics of diode type could be taken in vacuum in the temperature range 360–900 °C. Green light emission due to electroluminescence was observed from the junction area showing a maximum at a wavelength of 534 nm corresponding to a photon energy of 2.32 eV. The normalized emission spectrum was measured over the temperature range 320–440 °C with the device in air and was found independent of temperature and boron concentration.

Photo cells, photo cell arrays, and electrolytic devices using these cells and arrays

Abstract: A photo cell and a photo cell array which have high photoelectric conversion efficiency, little leakage current, long life, and high reliability, as well as a electrolytic device that employs the cell and array. The photo cell (1) comprises: a base material (2) consisting of p-type semiconductor; a light receiving section (3) being an integral spherical part of the base material (2) which protrudes outward from the surface of the base (2), and has an n-type semiconductor layer formed on the surface of said spherical part, so that a pn junction interface is formed between the base material (2) and the semiconductor layer; a front surface electrode (4) formed from conductive material in ohmic contact with a portion of the surface of the aforementioned sphere; and a lower or back electrode (5) formed from conductive material on the bottom of the aforementioned base material (2), to provide ohmic contact. The spherical shape of the photo cell (1) enables most of the surface of the sphere to be sensitive to light, with wider directivity than flat photo cells, and enables uniform sensitivity regardless of direction.

Semiconductor laser device including heat sink with pn junction

Abstract: A semiconductor laser device includes a semiconductor laser chip containing a diode having a polarity; a heat sink on which the semiconductor laser chip is mounted at an interface of the semiconductor laser chip and the heat sink, the heat sink including a pn junction generally parallel to the interface; and a block on which the heat sink is mounted, wherein the diode of the semiconductor laser chip and the pn junction are electrically connected in parallel and in opposite polarity so that the pn junction of the heat sink functions as a reverse current blocking diode for the semiconductor laser chip.

Method of forming a semiconductor device having a LC element

Abstract: An LC element with a pn junction layer formed near the surface of a p-Si substrate by forming an n + region having a predetermined shape and in a portion thereof additionally forming a p + region having the same shape, and with first and second electrodes formed over entire length on the surface of this pn junction layer; wherein the two electrodes respectively function as inductors and by using the pn junction layer with reverse bias, a distributed constant type capacitor is formed between these inductors, thereby providing excellent attenuation characteristics over a wide band, a semiconductor device including the LC element, and a method of manufacturing the LC element. This LC element and semiconductor device can be easily manufactured; in the case of manufacturing as a portion of an IC or LSI device, component assembly work in subsequent processing can be abbreviated, and by changing the capacitance of the distributed constant type capacitor according to requirements, the characteristics can be changed.

Semiconductor device and manufacture thereof

Abstract: PURPOSE:To obtain a P-type substrate semiconductor device which has a high withstand voltage and has no change in the withstand voltage with the passage of time by forming a hole trap level, in an oxide film on the surface of the substrate by casting electron beams. CONSTITUTION:By forming a hole trap level 16 in an oxide film 6 on the surface of a P-type semiconductor substrate 1 by casting electron beams, an N-type reverse layer 15 is formed on the surface of the P-type semiconductor substrate 1. This N-type inversion layer 15 expands a depletion layer 17 which is formed at the collector side of a PN junction when a reverse bias is applied, into a deep region of an element diffusion region, alleviates a curvature of the depletion layer 17, and increases the breakdown voltage. When movable ions in the oxide film 6 are drawn near to the boundary of the semiconductor substrate 1 in a high-temperature reverse bias test(BT), the N-type reverse layer 15 gets only a little bit deeper and there is little influence on the distribution of the ions in the depletion layer 17. Therefore, there is no change in the breakdown voltage.

Silicon carbide static induction transistor

Abstract: A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.

CCD solid state image device which has a semiconductor substrate with a P-type region with an N-type region formed therein by injection of arsenic

Abstract: In a CCD solid state image sensing device in which a photosensitive section is constructed by a photodiode formed by a PN junction between a first P-type well region and an N-type impurity diffusion region formed on an N-type silicon substrate, the N-type impurity diffusion region is formed by the ion implantation of single substance of arsenic (As). According to this CCD solid state image sensing device, a bright flaw on an image sensing screen, which is one of the defects encountered with an image sensing screen, can be reduced. Also, the n-type impurity diffusion region constructing the PN Junction can be reduced in size and the CCD solid state image sensing device itself can be made compact in size. Further, a method of manufacturing a CCD solid state image sensing device also is provided.

Phosphorous doping a semiconductor particle

Abstract: A method (10) of phosphorus doping a semiconductor particle using ammonium phosphate. A p-doped silicon sphere is mixed with a diluted solution of ammonium phosphate having a predetermined concentration. These spheres are dried (16, 18), with the phosphorus then being diffused (20) into the sphere to create either a shallow or deep p-n junction. A good PSG glass layer is formed on the surface of the sphere during the diffusion process. A subsequent segregation anneal process is utilized to strip metal impurities from near the p-n junction into the glass layer. A subsequent HF strip procedure is then utilized to removed the PSG layer. Ammonium phosphate is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirement.

Inversion charge modeling of SiGe PMOS and approaches to increasing the hole density in the SiGe channel

Abstract: A physical model of SiGe PMOS is presented. The condition for proper design ensuring the onset of strong inversion in the SiGe channel is modeled as a function of device structure. The threshold voltages and the inversion charge densities for both channels are also obtained. We show that the key to increasing the hole density in the SiGe channel lies in the reducing of the vertical electric field across the bottom Si/SiGe hetero-interface. Based on the modeling, a new bulk SiGe PMOS with a back pn junction sharing the depletion charge with the gate is proposed. Numerical simulation shows that the hole density in the SiGe channel of the back junction SiGe PMOS is comparable to that of the thin film SOI SiGe PMOS.

Method of manufacturing transistor with channel implant

Abstract: A semiconductor device includes a substrate having a first conduction type. A gate insulating film is provided on the substrate. A gate electrode is formed on the gate insulating film. A source region provided on the substrate has a second conduction type different from the first conduction type. A drain region provided on the substrate has the second conduction type. The source region and the drain region extend below the gate insulating film, and are located at respective sides of the gate electrode. A first region provided on the substrate has the first conduction type and extends below the gate insulating film. A second region provided on the substrate has the second conduction type, and extends below the first region. The second region connects with the first region via a pn junction. Third regions provided on the substrate have the first conduction type, and connect with the second region via respective pn junctions. A first one of the third regions extends between the second region and the source region. A second one of the third regions extends between the second region and the drain region. The first region has a width which is smaller than a sum of a width of a depletion layer caused by the pn junction with the second region and a width of a depletion layer caused by application of a voltage to the gate electrode. Third regions have a width which is greater than a sum of a width of a depletion layer caused by the source region and a width of a depletion layer caused by the pn junctions with the second region.

Organic Vapor Sensitivity In A Porous Silicon Device

Abstract: Organic vapor sensitive device using anodized porous silicon has been developed. The device consists of two pn junctions surrounded with the porous silicon layer as a vapor sensing element. The devices show an increase of current for exposure to thousands ppm of organic vapor at room temperature. A high sensitivity is observed for ethanol vapor. It is discussed that the adsorption of polar molecules induces a "soft" breakdown in the reverse biased pn junction.

Breakdown voltage enhancement of the p-n junction by self-aligned double diffusion process through a tapered SiO 2 implant mask

Abstract: The low doping region extension at the edge of the junction curvature is implemented with the self-aligned double diffusion process using a tapered SiO/sub 2/ implant mask. The p/sup +/-p-n diodes fabricated with the proposed double diffusion process have relaxed the surface electric field at the junction curvature and increased the breakdown voltage by 140 V, compared with the cylindrical p-n junction. It is also found that the breakdown voltage of the p/sup +/-p-n diodes having the field plate (FP) over the tapered oxide is 500 V, while that of the conventional p-n junction with the FP is 280 V. >

Calculation of Diffusion Component of Leakage Current in pn Junctions Formed in Various Types of Silicon Wafers (Intrinsic Gettering, Epitaxial, Silicon on Insulator)

Abstract: We derived a general analytical formula for the diffusion component of leakage current in pn junctions formed in various types of silicon wafers such as intrinsic gettering (IG), epitaxial (EPI), and silicon on insulator (SOI) wafers. From this analysis, it can be understood quantitatively that defect regions in IG wafers increase the diffusion current, although heavily doped regions in epitaxial wafers decrease the diffusion current, and in SOI wafers the diffusion current can be considerably reduced when there is a low recombination velocity at the Si/SiO2 interface.

IC protection structure having n-channel MOSFET with n-type resistor region

Abstract: A protection structure for integrated circuits with an n-channel MOS field-effect transistor has a more stable bipolar state, with the change to the bipolar state occurring fast. Below the drain region and the drain contact region an n-type resistor region doped more lightly than the drain region and the drain contact region is formed to provide the electrically conductive connection between the drain region and the drain contact region. When a positive voltage pulse is applied to the drain contact region, the n-channel MOS transistor will go into a bipolar operating state upon reaching the drain-source or drain-substrate breakdown voltage. The conductor paths are typically connected to ground. The n-well forms a series resistor between the drain region and the drain contact region of the respective transistor. It also forms a pn junction between the drain region and the channel, the collector pn junction, which extends deep into the substrate. Because of the series resistance of this n-well, during the change to the bipolar state, contractions of the current occurring at the pn junction are prevented. In the bipolar state, the transistor can absorb more power than with conventional arrangements. By connecting two or more transistors in parallel, the current is distributed even further, so that the power can be absorbed by both transistors, since the dissipation is distributed over an even larger area.