Showing papers on "Tunnel field-effect transistor published in 2014"

Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain

Abstract: In this paper, we have demonstrated that overlapping the gate on the drain can suppress the ambipolar conduction, which is an inherent property of a tunnel field effect transistor (TFET). Unlike in the conventional TFET where the gate controls the tunneling barrier width at both source-channel and channel-drain interfaces for different polarity of gate voltage, overlapping the gate on the drain limits the gate to control only the tunneling barrier width at the source-channel interface irrespective of the polarity of the gate voltage. As a result, the proposed overlapping gate-on-drain TFET exhibits suppressed ambipolar conduction even when the drain doping is as high as \(1 \times 10^{19}\) cm \(^{-3}\) .

Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance

Abstract: In this paper, we have investigated the effect of drain doping profile on a double-gate tunnel field-effect transistor (DG-TFET) and its radio-frequency (RF) performances. Lateral asymmetric drain doping profile suppresses the ambipolar behavior, improves OFF-state current, reduces the gate-drain capacitance, and improves the RF performance. Further, placing the high-density layer in the channel near the source-channel junction, a reduction in the width of depletion region, improvement in ON-state current (I ON ), and subthreshold slope are analyzed for this asymmetric drain doping. However, it also improves many RF figures of merit for the DG-TFET. Furthermore, lateral asymmetric doping effects on RF performances are also checked for the various channel length. Therefore, this paper would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. So, the RF figures of merit for the DG-TFET are analyzed in terms of transconductance (g m ), unit-gain cutoff frequency (f T ), maximum frequency of oscillation (f max ), and gain bandwidth product. For this, the RF figures of merit have been extracted from the V-parameter matrix generated by performing the small-signal ac analysis. Technology computer-aided design simulations have been performed by 2-D ATLAS, Silvaco International, Santa Clara, CA, USA.

In-Built N + Pocket p-n-p-n Tunnel Field-Effect Transistor

Abstract: The source-pocket (p-n-p-n) tunnel field effect transistor (TFET) has a narrow and highly doped N + pocket layer between the source and channel to enhance the overall performance of the conventional p-i-n TFET. However, realizing this, N + pocket increases the fabrication complexity since either an epitaxial growth in vertical TFETs or an implantation in planar TFETs is required to create the N + pocket. In this letter, using the charge plasma concept, we propose a technique to realize an in-built N + pocket without the need for a separate implantation. We demonstrate using 2-D simulations that the proposed in-built N + pocket p-n-p-n TFET exhibits a higher I ON (~20 times) and a steeper subthreshold swing (25 mV/decade) as compared with the conventional p-i-n TFET. Our approach overcomes the difficulty of creating a narrow N + pocket doping and thus makes the p-n-p-n TFET more attractive in carrying on with the scaling trend.

Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

Abstract: This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1- μm gate length device shows on current in excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~ 0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Abstract: Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si0.3Ge0.7, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT=2 nm) and dielectric, HfO2 at VGS=1 V and temperature of 300 K have ION of 0.02-12.5 mA/μm, ION/IOFF of 105-1012, and subthreshold swing (average) of 16-74 mV/decade.

A Novel Barrier Controlled Tunnel FET

Abstract: A novel structure of tunnel field-effect transistor (FET) is introduced with the gate composed of three segments of different work functions. The tunnel current is controlled by an in channel potential barrier as well as the source-channel tunnel junction bandgap, which combines the merits of both bandgap-controlled tunnel FET and barrier-controlled traditional MOSFET. Intuitive explanation is provided for this novel device structure. The performance enhancement is confirmed by numerical simulation with carbon nanotube as the channel material. This structure is especially suitable for bandgap tunable ballistic transport materials (e.g., carbon nanotube and graphene nanoribbon).

Assessment of field-induced quantum confinement in heterogate germanium electron-hole bilayer tunnel field-effect transistor

Abstract: The analysis of quantum mechanical confinement in recent germanium electron–hole bilayer tunnel field-effect transistors has been shown to substantially affect the band-to-band tunneling (BTBT) mechanism between electron and hole inversion layers that constitutes the operating principle of these devices. The vertical electric field that appears across the intrinsic semiconductor to give rise to the bilayer configuration makes the formerly continuous conduction and valence bands become a discrete set of energy subbands, therefore increasing the effective bandgap close to the gates and reducing the BTBT probabilities. In this letter, we present a simulation approach that shows how the inclusion of quantum confinement and the subsequent modification of the band profile results in the appearance of lateral tunneling to the underlap regions that greatly degrades the subthreshold swing of these devices. To overcome this drawback imposed by confinement, we propose an heterogate configuration that proves to suppress this parasitic tunneling and enhances the device performance.

Analytical modelling and simulation of single-gate SOI TFET for low-power applications

Abstract: In this article, a new two-dimensional (2-D) analytical model of the single-gate (SG) silicon-on-insulator (SOI) tunnel field effect transistors (TFETs) is proposed. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. Analytical expressions for surface potential and electric field are derived. The validity of the proposed model is tested for device scaled to 18-nm length and the analytical results are compared with Technology Computer Aided Design (TCAD) simulations.

Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor

Abstract: In this paper, the analog performance of a Si double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V semiconductor compound, indium aluminium arsenide. The analog performance parameters are extracted using device simulations and also compared with the Si JLTFET. We show that III–V JLTFET delivers much better performance parameters, in comparison to Si JLTFET, which includes transconductance generation efficiency (Gm/ID), intrinsic gain (GmRo) and unity gain frequency (fT) along with various gate capacitances.

Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length

Abstract: We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths. The devices consisted of single InGaAs nanowires with a diameter of 30 nm grown on p-type Si(111) substrates. The switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (VDS) of 0.10 V. Also, pinch-off behavior appeared at moderately low VDS, below 0.10 V. Reducing the channel length of the transistors attained a steep subthreshold slope (<60 mV/decade) and enhanced the drain current, which was 100 higher than that of the longer channels.

Dual material gate junctionless tunnel field effect transistor

Abstract: This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I ON/I OFF.

Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

Abstract: In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor (TFET) using HfO2 as a gate dielectric. The device principle and performance are investigated using a 2D simulator. During this work, we investigated the transfer characteristics, output characteristics, transconductance, Gm, output conductance, GD, and C–V characteristics of our proposed device. Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in ION of ∼0.23 mA μm−1, IOFF of ∼2.2 × 10−17 A μm−1, ION/IOFF of ∼1013, sub-threshold slope (SS) of ∼12 mV dec−1, DIBL of ∼93 mV V−1 and Vth of ≃0.11 V at room temperature and VDD of 0.7 V. This indicates that the H-JLTFET can play an important role in the further development of low power switching applications.

An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

Abstract: In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

Charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor: design and performance

Abstract: A double-gate charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor (NC-JLTFET) using a ferroelectric gate stack is proposed. Structurally, the NC-JLTFET consists of a heavily doped n-type silicon (Si) channel with two distinctive gates (control gate and fixed source gate). The fixed source gate accounts for the charge-plasma (hole plasma) formation which results in surrogate p-type doping by using work-function engineering. It induces a uniform p-region on the source side on the n-type doped Si film having a thickness less than the Debye length (L D). The key attribute of the NC-JLTFET is the ferroelectric gate stack which is employed as a control gate resulting in NC behaviour due to positive feedback among the electric dipoles in the ferroelectric material. The NC-JLTFET endeavours to achieve a super-steep sub-threshold slope, a paramount boost in drive current and a substantial enhancement in peak transconductance (g m) than the JLTFET. Meanwhile, it embraces the inherent advantages of the charge-plasma junctionless structure. Thus, it avails itself of a simple fabrication process flow and high immunity against process variations and random dopant fluctuations.

Analog performance of double gate junctionless tunnel field effect transistor

Abstract: For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor (DG-JLTFET) and the results are compared with the conventional n-type double gate tunnel field effect transistor (DG-TFET) counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.

Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique

Abstract: In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and shortchannel SBTFET .

Negative Capacitance Tunnel Field Effect Transistor: A Novel Device with Low Subthreshold Swing and High ON Current

Abstract: In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device effectively combines two different mechanisms of lowering the sub threshold swing (SS) for a transistor garnering a further lowered one compared to conventional TFET. A simple yet accurate analytical tunnel current model for the proposed device is also presented here. The developed analytical model demonstrates high ON current at low $V_{GS}$ and exhibits lower SS.

Negative Capacitance Tunnel Field Effect Transistor: A Novel Device with Low Subthreshold Swing and High on Current

Abstract: In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device effectively combines two different mechanisms of lowering the sub threshold swing (SS) for a transistor garnering a further lowered one compared to conventional TFET. A simple yet accurate analytical tunnel drain current model for the proposed device is also presented here. The developed analytical model demonstrates high ON current at low VGS and exhibits lower SS. This paper also provides physics based explanation behind the improvement in the SS for the proposed device over TFET.

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

Abstract: We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two different work functions (gateD 4.2 eV, gate1 D 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 10 6 A/ m, the off current remains as low as 9.1 10 14 A/ m. So ION/IOFF ratio of ' 10 8 is achieved. Point subthreshold swing has also been reduced to a value of ' 41 mV/decade for TiO2 gate material.

Impact of gate leakage considerations in tunnel field effect transistor design

Abstract: In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods for reducing the gate leakage, we show that if the gate tunneling leakage is not considered, even for these two methods, the overall TFET off-state current will be significantly underestimated. Our results demonstrate the need to carefully account for the gate leakage in the design of TFETs just as it is done for the conventional nanoscale MOSFETs.

Impact of gate leakage considerations in tunnel field effect transistor design

Abstract: In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-? gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods for reducing the gate leakage, we show that if the gate tunneling leakage is not considered, even for these two methods, the overall TFET off-state current will be significantly underestimated. Our results demonstrate the need to carefully account for the gate leakage in the design of TFETs just as it is done for the conventional nanoscale MOSFETs.

Planar graphene tunnel field-effect transistor

Abstract: We propose a concept for a graphene tunnel field-effect transistor The main idea is based on the use of two graphene electrodes with zigzag termination divided by a narrow gap under the influence of the common gate Our analysis shows that such device will have a pronounced switching effect at low gate voltage and high on/off current ratio at room temperature

Tunnel field-effect transistor and method for fabricating the same

Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation

Abstract: A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is reported in this letter. By varying the position of the grain boundary (GB) in the channel, the performance of the proposed device is evaluated using calibrated 2-D simulations. Our results show the possibility of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with low OFF-state current and low subthreshold swing compared with the thin-film transistors. By introducing the source N + pocket doping, it is also shown that the proposed single GB PNPN TFET exhibits enhanced ON-state current, making it suitable for low power display applications, including the driver circuits.

A Novel Fin Electron–Hole Bilayer Tunnel Field-Effect Transistor

Abstract: A novel fin electron–hole bilayer tunnel field-effect transistor (FinEHBTFET) is proposed and investigated by simulation. In this structure, a narrow fin is placed at the middle of a conventional p+-i-n + tunnel field-effect transistor, and two separate gates formed on left and right sides of the fin are used to control the channel. The FinEHBTFET achieves drive current when band-to-band tunneling happens between the bias-induced electron–hole bilayer at the two sides of the fin. The FinEHBTFET shows a high $I_{{\bf on}}/I_{{\bf off}}$ ratio more than 106, and an average SS of 3 mV/dec over three decades of drain current.

High performance tunnel field-effect transistor by gate and source engineering.

Abstract: As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high ION/IOFF ratio (~107) at VDS = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ~108 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec−1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Tunnel field-effect transistor and method for fabrictaing the same

Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.

P-type double gate junctionless tunnel field effect transistor

Abstract: We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor (P-DGJLTFET) and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET Together with a high-k dielectric material (TiO2) of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high ION of ~03 mA/μm, a low IOFF of ~30 fA/μm, a high ION/IOFF ratio of ~1 × 1010, a subthreshold slope (SS) point of ~23 mV/decade, and an average SS of ~49 mV/decade at a supply voltage of −1 V and at room temperature, which indicates that P-DGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits