Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Patent
Field programmable gate array
TL;DR: A field programmable gate array (FPGA) as discussed by the authors consists of a plurality of circuit blocks each having logic circuits, at least one spare circuit block having logic circuit, and a set of interconnections including at least a connecting element disposed on the interconnection of the set of circuits which turns its status from a turned on state to a turned off state or vice versa when programmed.
Patent
Transfer film and process for producing organic electroluminescent device using the same
TL;DR: In this article, a transfer film comprising a base film, a transfer layer, and a transfer auxiliary layer is formed between the base film and the transfer layer so as to be in contact with at least the transferred layer.
Proceedings ArticleDOI
On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation
TL;DR: This paper proposes to reuse dedicated bus-based test access mechanisms for real-time debug data transfer in post-silicon validation by significantly increases debug bandwidth with negligible routing overhead.
Patent
Dual function data register
TL;DR: In this paper, a dual-function serial and parallel data register with integrated program verify functionality is presented, where the master and slave latching circuits of the dual function data register can concurrently store two different words of data.
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Laminated semiconductor substrate process for producing the same
TL;DR: In this paper, an ion-implanted substrate is fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 μm with a solution having an etching effect on a surface of an active layer of a bonded substrate.