Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
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TLDR
In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.Abstract:
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.read more
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Patent
Semiconductor devices and methods of manufacturing the same
TL;DR: In this article, a gate pattern and a source/drain region are formed at both sides of the gate pattern, and the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source and drain region, and forming a second insulation layer covering the entire surface of the substrate.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Semiconductor structure and method for manufacturing the same
TL;DR: In this article, a method for manufacturing a semiconductor structure, comprising of a mask layer to cover the metal interconnect liners and forming openings, which expose the metal internals on the mask layer, is presented.
References
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Proceedings ArticleDOI
From the future Si technology perspective: Challenges and opportunities
TL;DR: Key drivers for silicon-based nano-electronics as well as research directions will be reviewed from viewpoints of system, memory, logic and emerging Si technologies.
Patent
Electronic device and manufacturing thereof
Ralf Otremba,Josef Hoeglauer +1 more
TL;DR: In this article, a power semiconductor chip is attached to a carrier, and the body is formed of an electrically insulating material covering the power SINR chip, and side faces extend from the first plane to the second plane, at least one of the multiple contact elements has a cross section in a direction orthogonal to the first planes that is longer than 60% of the distance between the first and second planes.
Patent
Method and apparatus providing optical input/output through the back side of an integrated circuit die
Mario J. Paniccia,Valluri R. Rao +1 more
TL;DR: In this article, a heat sink including a light source and an optical assembly is thermally and optically coupled to the back side of the integrated circuit die, and the deflected modulated light beam is routed and directed to the optical demodulators to realize optical input/output.
Proceedings ArticleDOI
Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm
Sarunya Bangsaruntip,Amlan Majumdar,Guy M. Cohen,Sebastian Engelmann,Y. Zhang,M. Guillorn,Lynne Gignac,S. Mittal,W. Graham,Eric A. Joseph,D. Klaus,Josephine B. Chang,Eduard A. Cartier,Jeffrey W. Sleight +13 more
TL;DR: In this article, the first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm were demonstrated.
Proceedings ArticleDOI
CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits
Shashikanth Bobba,Ashutosh Chakraborty,Olivier P. Thomas,Perrine Batude,Thomas Ernst,O. Faynot,David Z. Pan,Giovanni De Micheli +7 more
TL;DR: This work proposes two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacks).